MC10E451, MC100E451 5 V ECL 6-Bit D Register Differential Data and Clock Description The MC10E/100E451 contains six D-type flip-flops with www.onsemi.com single-ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Master Reset (MR) input resets all Q outputs to LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of PLCC28 the inputs. Because of the edge triggered flip-flop nature of the device FN SUFFIX simultaneously opening both the clock and data inputs will result in an CASE 77602 output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below V . CC The V pin, an internally generated voltage supply, is available to BB MARKING DIAGRAM* this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB 128 V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. BB MCxxxE451FNG The 100 Series contains temperature compensation. AWLYYWW Features Differential Inputs: Data and Clock xxx = 10 or 100 V Output BB A = Assembly Location 1100 MHz Min. Toggle Frequency WL = Wafer Lot YY = Year Asynchronous Master Reset WW = Work Week G = Pb-Free Package PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V CC EE *For additional marking information, refer to NECL Mode Operating Range: Application Note AND8002/D. V = 0 V with V = 4.2 V to 5.7 V CC EE Internal Input 50 k Pulldown Resistors ESD Protection: ORDERING INFORMATION > 2 kV Human Body Model Device Package Shipping > 200 V Machine Model MC10E451FNG PLCC28 37 Units / Tube Transistor Count = 348 Devices (Pb-Free) Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test MC10E451FNR2G PLCC28 500 Tape & Reel Flammability Rating: UL 94 V0 0.125 in, (Pb-Free) Oxygen Index: 28 to 34 MC100E451FNG PLCC28 37 Units / Tube Moisture Sensitivity: Level 3 (Pb-Free) (Pb-Free) (For Additional Information, see Application Note AND8003/D) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer These Devices are Pb-Free, Halogen Free and are RoHS Compliant to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 10 MC10E451/DMC10E451, MC100E451 D D D D D D V 5 5 4 4 3 3 CCO D 0 Q D 0 D 0 R 25 24 23 22 21 20 19 18 CLK Q D 26 1 5 D Q 1 D 1 R 17 V Q 27 BB 4 D 2 Q D 2 D 2 16 CLK 28 V CC R D 3 1 D Q 15 3 V Q EE MC10E451/MC100E451 3 D 3 R 14 MR 2 V D CCO 4 D Q 4 D 4 R 13 NC 3 Q 2 D 5 Q D 5 D D 5 4 12 0 Q 1 R CLK 567 89 10 11 CLK MR D D D D D V Q 0 1 1 2 2 CCO 0 V * All V and V pins are tied together on the die. BB CC CCO Figure 2. Logic Diagram Warning: All V , V , and V pins must be externally con- CC CCO EE nected to Power Supply to guarantee proper operation. Figure 1. 28-Lean Pinout Assignment (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION D D , D D ECL Differential Data Input 0 5 0 5 CLK, CLK ECL Differential Clock Input MR ECL Master Reset Input Q Q ECL Data Outputs 0 5 V Reference Voltage Output BB V , V Positive Supply CC CCO V Negative Supply EE NC No Connect www.onsemi.com 2