5 VECL 2Input Differential AND/NAND MC10EL05, MC100EL05 Description The MC10EL/100EL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the E404 device with higher www.onsemi.com performance capabilities. With propagation delays and output transition times significantly faster than the E404, the EL05 is ideally suited for those applications which require the ultimate in AC performance. Because a negative 2-input NAND is equivalent to a 2-input OR 8 function, the differential inputs and outputs of the device allows the EL05 1 to also be used as a 2-input differential OR/NOR gate. The differential inputs employ clamp circuitry so that under open input SOIC8 conditions (pulled down to V ) the input to the AND gate will be EE D SUFFIX HIGH. In this way, if one set of inputs is open, the gate will remain active CASE 75107 to the other input. The 100 Series contains temperature compensation. Features MARKING DIAGRAM* 275 ps Propagation Delay 8 8 ESD Protection: HEL05 KEL05 ALYW ALYW > 1 kV Human Body Model, > 100 V Machine Model 1 1 PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V H = MC10 CC EE K = MC100 NECL Mode Operating Range: A = Assembly Location V = 0 V with V = 4.2 V to 5.7 V CC EE L = Wafer Lot Internal Input Pulldown Resistors Y = Year W = Work Week Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test = Pb-Free Package Moisture Sensitivity (Note: Microdot may be in either location) For Additional Information, see Application Note AND8003/D *For additional marking information, refer to Flammability Rating: Application Note AND8002/D. UL 94 V0 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 44 devices ORDERING INFORMATION These Devices are Pb-Free, Halogen Free and are RoHS Compliant Device Package Shipping MC10EL05DR2G SOIC8 2500 / (Pb-Free) Tape & Reel SOIC8 MC100EL05DG 98 Units / Tube (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2021 Rev. 8 MC10EL05/DMC10EL05, MC100EL05 Table 1. TRUTH TABLE D0 D1 D0 D1 Q Q L L H H L H D 1 8 V L H H L L H 0 CC H L L H L H D 2 7 0 Q H H L L H L Table 2. PIN DESCRIPTION D 3 6 Q 1 PIN Function D0, D0 D1, D1 ECL Data Inputs D 4 5 V 1 EE Q, Q ECL Data Outputs V Positive Supply CC Figure 1. Logic Diagram and Pinout V Negative Supply EE Assignment Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 V CC EE V NECL Mode Power Supply V = 0 V 8 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 190 C/W JA 500 lfpm 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 41 to 44 C/W JC T Wave Solder (Pb-Free) <2 to 3 sec 260C 265 C sol NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. Input and output parameters vary 1:1 with V . V can vary +0.25 V / 0.5 V. CC EE 2. Outputs are terminated through a 50 resistor to V 2.0 V. CC 3. V min varies 1:1 with V , V max varies 1:1 with V . The V range is referenced to the most positive side of the differential input IHCMR EE IHCMR CC IHCMR signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V and 1.0 V. PP(min) www.onsemi.com 2