MC100EL14 5 V ECL 1:5 Clock Distribution Chip Description The MC100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The V pin, an BB www.onsemi.com internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also BB BB rebias AC coupled inputs. When used, decouple V and V via a BB CC 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V should be left open. BB The EL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed SOIC20 WB system clock. When LOW (or left open and pulled LOW by the input DW SUFFIX pulldown resistor) the SEL pin will select the differential clock input. CASE 751D05 The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is MARKING DIAGRAM enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the 20 negative edge of the clock input. 100EL14 Features AWLYYWWG 50 ps Output-to-Output Skew Synchronous Enable/Disable 1 Multiplexed Clock Input The 100 Series Contains Temperature Compensation A = Assembly Location PECL Mode Operating Range: V = 4.2 V to 5.7 V CC WL = Wafer Lot with V = 0 V EE YY = Year NECL Mode Operating Range: V = 0 V WW = Work Week CC G = Pb-Free Package with V = 4.2 V to 5.7 V EE Q Output will Default LOW with Inputs Open or at V EE *For additional marking information, refer to Application Note AND8002/D. Internal Input Pull-down Resistors on All Inputs, Pull-up Resistors on Inverted Inputs This Device is Pb-Free, Halogen Free and is RoHS Compliant ORDERING INFORMATION Device Package Shipping MC100EL14DWG SOIC20 WB 38 Units/Tube (Pb-Free) Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 9 MC100EL14/DMC100EL14 V EN V NC SCLK CLK CLK V SEL V CC CC BB EE Table 1. PIN DESCRIPTION 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION CLK, CLK ECL Diff Clock Inputs 1 0 SCLK ECL Scan Clock Input D Q EN ECL Sync Enable SEL ECL Clock Select Input Q Q ECL Diff Clock Outputs 0 4, 0 4 1 2 3 4 5678 9 10 V Reference Voltage Output BB V Positive Supply Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 CC V Negative Supply EE * All V pins are tied together on the die. CC NC No Connect Warning: All V and V pins must be externally connected to CC EE Power Supply to guarantee proper operation. Table 2. FUNCTION TABLE Figure 1. Logic Diagram and Pinout Assignment CLK* SCLK* SEL* EN* Q L X L L L H X L L H X L H L L X H H L H X X X H L (Note ) 1. On next negative transition of CLK or SCLK **Pins will default low when left open. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charge Device Model > 4 kV Moisture Sensitivity (Note 2) Pb-Free Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 303 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. www.onsemi.com 2