N74F00D,623 Nexperia

INTEGRATED CIRCUITS 74F00 Quad 2-input NAND gate Product specification 1990 Oct 04 IC15 Data Handbook Philips Semiconductors Product specification Quad 2-input NAND gate 74F00 FEATURE PIN CONFIGURATION Industrial temperature range available (40C to +85C) D0a 1 14 V CC D0b 2 13 D3b TYPE TYPICAL TYPICAL Q0 3 12 D3a PROPAGATION SUPPLY CURRENT DELAY (TOTAL) D1a 4 11 Q3 74F00 3.4ns 4.4mA D1b 5 10 D2b Q1 6 9 D2a GND 7 8 Q2 SF00001 ORDERING INFORMATION ORDER CODE DESCRIPTION PKG DWG COMMERCIAL RANGE INDUSTRIAL RANGE V = 5V 10%, T = 0C to +70C V = 5V 10%, T = 40C to +85C CC amb CC amb 14-pin plastic DIP N74F00N I74F00N SOT27-1 14-pin plastic SO N74F00D I74F00D SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb Data inputs 1.0/1.0 20A/0.6mA Qn Data output 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. LOGIC DIAGRAM FUNCTION TABLE 1 INPUTS OUTPUT D0a 3 2 Q0 D0b Dna Dnb Qn 4 D1a L L H 6 5 Q1 D1b L H H 9 D2a 8 H L H Q2 10 D2b H H L 12 11 V = Pin 14 CC D3a Q3 13 NOTES: GND = Pin 7 D3b H = High voltage level SF00002 L = Low voltage level LOGIC SYMBOL IEC/IEEE SYMBOL & 1 3 2 12 4 5 9 101213 4 6 5 D0a D0bD1a D1bD2a D2b D3a D3b 9 8 Q0 Q1 Q2 Q3 10 12 11 36 8 11 13 V = Pin 14 CC GND = Pin 7 SF00003 SF00004 October 4, 1990 2 853-0325 00623