MC10E151, MC100E151 5 VECL 6Bit D Register Description The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the www.onsemi.com slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW. The 100 Series contains temperature compensation. Features 1100 MHz Min. Toggle Frequency Differential Outputs PLCC28 Asynchronous Master Reset FN SUFFIX CASE 77602 Dual Clocks PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: MARKING DIAGRAM* V = 0 V with V = 4.2 V to 5.7 V CC EE 1 Internal Input 50 k Pulldown Resistors ESD Protection: Human Body Model > 2 kV MCxxxE151FNG Machine Model > 200 V AWLYYWW Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: 3 (Pb-Free) For Additional Information, see Application Note AND8003/D xxx = 10 or 100 Flammability Rating: UL 94 V0 0.125 in, A = Assembly Location WL = Wafer Lot Oxygen Index: 28 to 34 YY = Year Transistor Count = 304 devices WW = Work Week These Devices are Pb-Free, Halogen Free and are RoHS Compliant G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC10E151FNG PLCC28 37 Units/Tube (Pb-Free) MC10E151FNR2G PLCC28 500/Tape & Reel (Pb-Free) MC100E151FNG PLCC28 37 Units/Tube (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 10 MC10E151/DMC10E151, MC100E151 MR CLK2 CLK1 NC V Q Q CCO 5 5 Table 1. PIN DESCRIPTION PIN FUNCTION 25 24 23 22 21 20 19 D 26 Q 5 18 4 D D ECL Data Inputs 0 5 CLK1, CLK2 ECL Clock Inputs D 27 Q 4 17 4 MR ECL Master Reset 28 D 16 V 3 CC Q Q , Q Q ECL Differential Outputs 0 5 0 5 1 V V , V Positive Supply 15 Q EE CC CCO 3 V Negative Supply EE D 2 14 Q 2 3 NC No Connect D 3 13 Q 1 2 D 4 0 Q 12 2 567 8 9 10 11 NC V Q Q Q Q V CCO 0 0 1 1 CCO * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 1. Pinout: PLCC28 (Top View) Q Table 2. FUNCTION TABLE D D 0 0 Q 0 MR Qn R 1 Reset L D D Q 1 1 0 Operational H Q 1 R Q D D 2 2 Q 2 R D D Q 3 3 Q R 3 D Q 4 D 4 Q R 4 D D Q 5 5 Q 5 R CLK1 CLK2 MR Figure 2. Logic Diagram www.onsemi.com 2