M74HCT373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING HIGH SPEED: t = 19ns (TYP.) at V = 4.5V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 6mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t PLH PHL ORDER CODES PIN AND FUNCTION COMPATIBLE WITH PACKAGE TUBE T & R 74 SERIES 373 DIP M74HCT373B1R SOP M74HCT373M1R M74HCT373RM13TR DESCRIPTION TSSOP M74HCT373TTR The M74HCT373 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated 2 with sub-micron silicon gate C MOS technology. level) and when OE is in high level the outputs will This 8-BIT D-Type latches is controlled by a latch be in a high impedance state. enable input (LE) and output enable input (OE). The 3-State output configuration and the wide While the LE input is held at a high level, the Q choice of outline make bus organized system outputs will follow the data input. When the LE is simple. taken low, the Q outputs will be latched at the logic All inputs are equipped with protection circuits level of D input data. against static discharge and transient excess While the OE input is at low level, the eight outputs voltage. will be in a normal logic state (high or low logic PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 Obsolete Product(s) - Obsolete Product(s)M74HCT373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW) 2, 5, 6, 9, 12, Q0 to Q7 3 State Outputs 15, 16, 19 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 11 LE Latch Enable Input 10 GND Ground (0V) 20 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS OE LE D Q H XXZ L L X NO CHANGE (*) LHL L LH H H X: Dont Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. LOGIC DIAGRAM 2/11 Obsolete Product(s) - Obsolete Product(s)