Product Information

M74HCT573TTR

M74HCT573TTR electronic component of STMicroelectronics

Datasheet
Latches Octal "D" Latch

Manufacturer: STMicroelectronics
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete
Availability Price Quantity
0 - WHS 1

MOQ : 1
Multiples : 1

Stock Image

M74HCT573TTR
STMicroelectronics

1 : USD 0.2659
N/A

Obsolete
0 - WHS 2


Multiples : 1

Stock Image

M74HCT573TTR
STMicroelectronics

N/A

Obsolete
0 - WHS 3


Multiples : 1

Stock Image

M74HCT573TTR
STMicroelectronics

N/A

Obsolete
     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Type
Logic Family
Polarity
Quiescent Current
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Package / Case
Packaging
Series
Brand
Mounting Style
Number Of Channels
Number Of Input Lines
Supply Current - Max
Factory Pack Quantity :
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M74HCT573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING HIGH SPEED: t = 21ns (TYP.) at V = 4.5V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP BALANCED PROPAGATION DELAYS: t t PLH PHL SYMMETRICAL OUTPUT IMPEDANCE: I = I = 6mA (MIN) OH OL ORDER CODES PIN AND FUNCTION COMPATIBLE WITH PACKAGE TUBE T & R 74 SERIES 573 DIP M74HCT573B1R SOP M74HCT573M1R M74HCT573RM13TR DESCRIPTION TSSOP M74HCT573TTR The M74HCT573 is an high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated 2 with silicon gate C MOS technology. The 3-State output configuration and the wide This 8-BIT D-Type latches is controlled by a latch choice of outline make bus organized system enable input (LE) and output enable input (OE). simple. While the LE input is held at a high level, the Q The M74HCT573 is designed to directly interface 2 outputs will follow the data input precisely. When HSCMOS systems with TTL and NMOS the LE is taken low, the Q outputs will be latched components. precisely at the logic level of D input data. All inputs are equipped with protection circuits While the OE input is at low level, the eight outputs against static discharge and transient excess will be in a normal logic state (high or low logic voltage. level) and while OE is at high level the outputs will be in a high impedance state. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 Obsolete Product(s) - Obsolete Product(s)M74HCT573 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW) 2, 3, 4, 5, 6, D0 to D7 Data Inputs 7, 8, 9 12, 13, 14, Q0 to Q7 3 State Latch Outputs 15, 16, 17, 18, 19 11 LE Latch Enable Input 10 GND Ground (0V) 20 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS OE LE D Q H XXZ L L X NO CHANGE (*) LHL L LH H H X: Dont Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. LOGIC DIAGRAM 2/11 Obsolete Product(s) - Obsolete Product(s)

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
C-Max
C-Max (VA)
SG3
ST
ST MICROELECTRONICS
ST2
ST7
STM
STMICRELECTRONICS
STN

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