M74HCT74RM13TR STMicroelectronics

M74HCT74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED : f = 48MHz (TYP.) at V = 4.5V MAX CC LOW POWER DISSIPATION: I =2A(MAX.) at T =25C CC A COMPATIBLE WITH TTL OUTPUTS : V = 2V (MIN.) V = 0.8V (MAX) IH IL DIP SOP TSSOP BALANCED PROPAGATION DELAYS: t t PLH PHL SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) ORDER CODES OH OL PIN AND FUNCTION COMPATIBLE WITH PACKAGE TUBE T & R 74 SERIES 74 DIP M74HCT74B1R SOP M74HCT74M1R M74HCT74RM13TR DESCRIPTION TSSOP M74HCT74TTR The M74HCT74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with 2 silicon gate C MOS technology. The M74HCT74 is designed to directly interface 2 A signal on the D INPUT (nD) is transferred on the HSCMOS systems with TTL and NMOS Q OUTPUT during the positive going transition of components. the clock pulse. CLEAR (CLR) and PRESET (PR) All inputs are equipped with protection circuits are independent of the clock and accomplished by against static discharge and transient excess a low on the appropriate input. voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/10 Obsolete Product(s) - Obsolete Product(s)M74HCT74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION Asynchronous Reset - 1,13 1CLR, 2CLR Direct Input 2, 12 1D, 2D Data Inputs Clock Input 3, 11 1CK, 2CK (LOW-to-HIGH, Edge-Triggered) Asynchronous Set - Direct 4, 10 1PR, 2PR Input 5, 9 1Q, 2Q True Flip-Flop Outputs Complement Flip-Flop 6, 8 1Q, 2Q Outputs 7 GND Ground (0V) 14 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR DCK Q Q L H X X L H CLEAR H L X X H L PRESET L L X X H H ---- H H L L H ---- H H H H L ---- HH X Q Q NO CHANGE n n X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10 Obsolete Product(s) - Obsolete Product(s)