M74HCT574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
HIGH SPEED:
f = 50MHz (TYP.) at V = 4.5V
MAX CC
LOW POWER DISSIPATION:
I = 4A(MAX.) at T =25C
CC A
COMPATIBLE WITH TTL OUTPUTS :
V = 2V (MIN.) V = 0.8V (MAX)
IH IL
DIP SOP TSSOP
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 6mA (MIN)
OH OL
BALANCED PROPAGATION DELAYS:
t t
PLH PHL ORDER CODES
PIN AND FUNCTION COMPATIBLE WITH
PACKAGE TUBE T & R
74 SERIES 574
DIP M74HCT574B1R
SOP M74HCT574M1R M74HCT574RM13TR
DESCRIPTION
TSSOP M74HCT574TTR
The M74HCT574 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
INVERTING fabricated with sub-micron silicon
The output control does not affect the internal
2
gate C MOS technology.
operation of flip-flops; that is, the old data can be
This 8 bit D-TYPE FLIP FLOP is controlled by a
retained or the new data can be entered even
clock input (CK) and an output enable input (OE).
while the outputs are off.
On the positive transition of the clock, the Q
All inputs are equipped with protection circuits
outputs will be set to the logic state that were
against static discharge and transient excess
setup at the D inputs.
voltage.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is in high level the outputs will
be in a high impedance state.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001 1/11
Obsolete Product(s) - Obsolete Product(s)M74HCT574
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1OE 3 State Output Enable
Input (Active LOW)
2, 3, 4, 5, 6, D0 to D7 Data Inputs
7, 8, 9
12, 13, 14, Q7 to Q0 3 State Outputs
15, 16, 17,
18, 19
11 CK Clock Input (LOW to
HIGH, edge triggered)
10 GND Ground (0V)
20 V Positive Supply Voltage
CC
TRUTH TABLE
INPUTS OUTPUT
OE CK D Q
H XXZ
L X NO CHANGE
LLL
LHH
X: Dont Care
Z: High Impedance
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
2/11
Obsolete Product(s) - Obsolete Product(s)