M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED : f = 80MHz (TYP.) at V = 6V MAX CC LOW POWER DISSIPATION: I =2A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC73B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC73M1R M74HC73RM13TR 74 SERIES 73 TSSOP M74HC73TTR DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K clear function is accomplished independently of FLIP FLOP WITH CLEAR fabricated with silicon the clock condition when the clear input (CLR) is 2 gate C MOS technology. taken low. Depending on the logic level applied to J and K All inputs are equipped with protection circuits inputs, this device changes state on the negative against static discharge and transient excess going transition of clock input pulse (CK). The voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 Obsolete Product(s) - Obsolete Product(s)M74HC73 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 5 1CK, 2CK Clock Input Asynchronous Reset 2, 6 1CLR, 2CLR Inputs 12, 9 1Q, 2Q True Flip-Flop Outputs Complement Flip-Flop 13, 8 1Q, 2Q Outputs 1J, 2J, 1K, Synchronous Inputs 14, 7, 3, 10 2K Flip-Flop 1 and 2 11 GND Ground (0V) 4 Vcc Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR JK CK QQ L X X X L H CLEAR Q Q HL L NO CHANGE n n H L H L H ---- H H L H L ---- Q Q HHH TOGGLE n n Q Q HX X NO CHANGE n n X : Dont Care LOGIC DIAGRAM 2/11 Obsolete Product(s) - Obsolete Product(s)