DM74ALS573BWMX ON Semiconductor

DM74ALS573B Extended Temperature Octal D-Type Transparent Latch with 3-STATE Outputs April 1984 Revised February 2000 DM74ALS573B Extended Temperature Octal D-Type Transparent Latch with 3-STATE Outputs General Description Features These 8-bit registers feature totem-pole 3-STATE outputs Switching specifications at 50 pF designed specifically for driving highly-capacitive or rela- Switching specifications guaranteed over full tempera- tively low-impedance loads. The high-impedance state and ture and V range CC increased high-logic-level drive provide these registers with Advanced oxide-isolated, ion-implanted Schottky TTL the capability of being connected directly to and driving the process bus lines in a bus-organized system without need for inter- Functionally equivalent with DM74LS373 face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional Improved AC performance over DM74LS373 at approxi- bus drivers, and working registers. mately half the power The eight latches of the DM74ALS573B are transparent D- 3-STATE buffer-type outputs drive bus lines directly type latches. While the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set UP. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-imped- ance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF. Ordering Code: Order Number Package Number Package Description DM74ALS573BWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74ALS573BSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74ALS573BN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram 2000 Fairchild Semiconductor Corporation DS006226 www.fairchildsemi.comFunction Table Logic Diagram Output Enable D Output Control G Q LH H H LH L L LL X Q 0 HX X Z L = LOW State H = HIGH State X = Dont Care Z = High Impedance State Q = Previous Condition of Q 0 www.fairchildsemi.com 2 DM74ALS573B