M74HC573B1R STMicroelectronics

M74HC573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING HIGH SPEED: t = 13ns (TYP.) at V = 6V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 6mA (MIN) OH OL BALANCED PROPAGATION DELAYS: ORDER CODES t t PLH PHL PACKAGE TUBE T & R WIDE OPERATING VOLTAGE RANGE: V (OPR) = 2V to 6V DIP M74HC573B1R CC PIN AND FUNCTION COMPATIBLE WITH SOP M74HC573M1R M74HC573RM13TR 74 SERIES 573 TSSOP M74HC573TTR DESCRIPTION While the OE input is at low level, the eight outputs The M74HC573 is an high speed CMOS OCTAL will be in a normal logic state (high or low logic LATCH WITH 3-STATE OUTPUTS fabricated level) and while is at high level the outputs will be 2 with silicon gate C MOS technology. in a high impedance state. This 8-BIT D-Type latches is controlled by a latch The 3-State output configuration and the wide enable input (LE) and output enable input (OE). choice of outline make bus organized system While the LE input is held at a high level, the Q simple. All inputs are equipped with protection circuits outputs will follow the data input precisely. When LE is taken low, the Q outputs will be latched against static discharge and transient excess precisely at the logic level of D input data. voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12M74HC573 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1OE 3 State Output Enable Input (Active LOW) 2, 3, 4, 5, 6, D0 to D7 Data Inputs 7, 8, 9 12, 13, 14, Q0 to Q7 3 State Latch Outputs 15, 16, 17, 18, 19 11 LE Latch Enable Input 10 GND Ground (0V) 20 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS OE LE D Q H XXZ L L X NO CHANGE (*) LHL L LH H H X: Dont Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. LOGIC DIAGRAM 2/12