5962-9221701MRA Renesas

IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL IDT54/74FCT373T/AT/CT TRANSPARENT LATCH FEATURES: DESCRIPTION: Std., A, and C grades The FCT373Tis an octal transparent latch built using an advanced dual Low input and output leakage 1A (max.) metal CMOS technology. These octal latches have 3-state outputs and are CMOS power levels intended for bus oriented applications. The flip-flops appear transparent to True TTL input and output compatibility: the data when Latch Enable (LE) is high. When LE is low, the data that meets VOH = 3.3V (typ.) the set-up time is latched. Data appears on the bus when the Output Enable VOL = 0.3V (typ.) (OE) is low. When OE is high, the bus output is in the high-impedance state. High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permitlive insertio Available in the following packages: Industrial: SOIC, SSOP, QSOP Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D D D D D D D D O O O O O O O O G G G G G G G G LE OE O2 O3 O6 O7 O0 O1 O4 O5 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES DECEMBER 2016 1 DSC-5496/7IDT54/74FCT373T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCH MILITARY AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION 20 VCC OE 1 INDEX 19 O0 2 O7 3 2 D0 20 19 18 3 D7 1 4 18 D1 D7 D1 4 17 D6 5 17 O1 D6 O1 5 16 O6 6 16 O6 O2 O2 15 O5 6 7 15 D2 O5 D2 D5 7 14 D3 8 14 D5 9 10 11 12 13 D3 13 D4 8 O3 9 12 O4 LE 11 GND 10 LCC CERDIP/ SOIC/ SSOP/ QSOP TOP VIEW TOP VIEW (1) ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION Symbol Description Max Unit Pin Names Description (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V Dx Data Inputs (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V LE Latch Enable Input (Active HIGH) TSTG Storage Temperature 65 to +150 C OE Output Enable Input (Active LOW) IOUT DC Output Current 60 to +120 mA O x 3-State Outputs NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational (1) sections of this specification is not implied. Exposure to absolute maximum rating FUNCTION TABLE conditions for extended periods may affect reliability. No terminal voltage may exceed Inputs Outputs Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. Dx LE OE Ox 3. Output and I/O terminals only. HH L H LH L L XX H Z CAPACITANCE (TA = +25C, F = 1.0MHz) NOTE: 1. H = HIGH Voltage Level (1) Symbol Parameter Conditions Typ. Max. Unit X = Dont Care CIN Input Capacitance VIN = 0V 6 10 pF L = LOW Voltage Level Z = High Impedance COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 1. This parameter is measured at characterization but not tested. 2 O3 D0 GND O0 OE LE O4 VCC D4 O7