IDT54/74FCT374T/AT/CT FAST CMOS OCTAL D REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL D IDT54/74FCT374T/AT/CT REGISTER (3-STATE) FEATURES: DESCRIPTION: Std., A, and C grades The FCT374T is an 8-bit register built using an advanced dual metal Low input and output leakage 1A (max.) CMOS technology. These registers consist of eight D-type flip-flops with a CMOS power levels buffered common clock and buffered 3-state output control. When the output True TTL input and output compatibility: enable (OE) input is low, the eight outputs are enabled. When the OE input VOH = 3.3V (typ.) is high, the outputs are in the high-impedance state. VOL = 0.3V (typ.) Input data meeting the set-up and hold time requirements of the D inputs High Drive outputs (-15mA IOH, 48mA IOL) is transferred to the Q outputs on the low-to-high transition of the clock input. Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permitlive insertio Available in the following packages: Industrial: SOIC, SSOP, QSOP Military: CERDIP, LCC FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP D D D D D D D D CP CP CP CP CP CP CP CP Q QQQ Q QQ Q OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 2009 1 2009 Integrated Device Technology, Inc. DSC-5491/7IDT54/74FCT374T/AT/CT FAST CMOS OCTAL D REGISTER (3-STATE) MILITARY AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION INDEX VCC OE 1 20 19 Q0 2 Q7 3 2 20 19 D0 18 3 D7 1 4 18 D1 D7 D1 4 17 D6 5 17 Q1 D6 Q1 Q6 5 16 6 16 Q2 Q6 Q5 Q2 6 15 7 15 D2 Q5 D2 D5 7 14 D3 8 14 D5 9 10 11 12 13 D4 D3 8 13 Q3 9 12 Q4 CP 11 GND 10 CERDIP/ SOIC/ SSOP/ QSOP LCC TOP VIEW TOP VIEW (1) ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION Symbol Description Max Unit Pin Names Description (2) VTERM Terminal Voltage with Respect to GND 0.5 to +7 V Dx D flip-flop data inputs (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V CP Clock Pulse for the register. Enters data on LOW-to- HIGH transition. TSTG Storage Temperature 65 to +150 C Q x 3-State Outputs (TRUE) IOUT DC Output Current 60 to +120 mA Q x 3-State Outputs (INVERTED) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause OE Active LOW 3-State Output Enable Input permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating (1) conditions for extended periods may affect reliability. No terminal voltage may exceed FUNCTION TABLE Vcc by +0.5V unless otherwise noted. Inputs Outputs Internal 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. Function OE CP Dx Qx Qx High-Z H L X Z N C HH X Z NC Load L LL H CAPACITANCE (TA = +25C, F = 1.0MHz) Register L HH L (1) Symbol Parameter Conditions Typ. Max. Unit H LZ H CIN Input Capacitance VIN = 0V 6 10 pF H HZ L COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 1. H = HIGH Voltage Level NOTE: X = Dont Care 1. This parameter is measured at characterization but not tested. L = LOW Voltage Level Z = High Impedance NC = No Change = LOW-to-HIGH transition 2 Q3 D0 Q0 GND OE CP Q4 VCC D4 Q7