M95040-DFDW6TP STMicroelectronics

M950x0-W M950x0-R M950x0-DF 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Datasheet - production data Features Compatible with SPI bus serial interface (Positive clock SPI modes) Single supply voltage: 2.5 V to 5.5 V for M950x0-W 1.8 V to 5.5 V for M950x0-R 1.7 V to 5.5 V for M95040-DF SO8 (MN) High-speed 20 MHz clock rate, 5 ms write time 150 mil width Memory array: 1/2/4 Kbit (128/256/512 bytes) of EEPROM Page size: 16 bytes Write protection by block: 1/4, 1/2 or whole memory Additional Write lockable Page (Identification page) TSSOP8 (DW) 169 mil width Enhanced ESD protection More than 4 million write cycles More than 200-year data retention Packages RoHS-compliant and Halogen-free (ECOPACK) Table 1. Device summary UFDFPN8 (MC) 2 x 3 mm Reference Part number M95040-W M950x0-W M95020-W M95010-W M95040-R M950x0-R M95020-R M95010-R M950x0-DF M95040-DF August 2014 DocID6512 Rev 13 1/46 This is information on a product in full production. www.st.comContents M950x0-W M950x0-R M950x0-DF Contents 1 Description . 6 2 Signal description . 8 2.1 Serial Data Output (Q) 8 2.2 Serial Data Input (D) 8 2.3 Serial Clock (C) . 8 2.4 Chip Select (S) 8 2.5 Hold (HOLD) 8 2.6 Write Protect (W) 9 2.7 V ground . 9 SS 2.8 Supply voltage (V ) . 9 CC 2.8.1 Operating supply voltage (V ) 9 CC 2.8.2 Device reset . 9 2.8.3 Power-up conditions . 10 2.8.4 Power-down 10 3 Connecting to the SPI bus . 11 3.1 SPI modes 12 4 Operating features . 13 4.1 Hold condition 13 4.2 Status register . 13 4.3 Data protection and protocol control 14 5 Memory organization . 15 6 Instructions . 16 6.1 Write Enable (WREN) . 17 6.2 Write Disable (WRDI) 18 6.3 Read Status Register (RDSR) . 19 6.3.1 WIP bit 19 6.3.2 WEL bit . 19 6.3.3 BP1, BP0 bits . 20 2/46 DocID6512 Rev 13