SPC560P40L1BEFBR STMicroelectronics

SPC560P34L1, SPC560P34L3 SPC560P40L1, SPC560P40L3 32-bit Power Architecture based MCU with 320 KB Flash memory and 20 KB RAM for automotive chassis and safety applications Datasheet production data Features Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h) Compliant with Power Architecture embedded category Variable Length Encoding (VLE) LQFP100 (14 x 14 x 1.4 mm) LQFP64 (10 x 10 x 1.4 mm) Memory organization Communications interfaces Up to 256 KB on-chip code flash memory 2 LINFlex channels (1 Master/Slave, 1 with ECC and erase/program controller Master only) Additional 64 (4 16) KB on-chip data Up to 3 DSPI channels with automatic chip flash memory with ECC for EEPROM select generation (up to 8/4/4 chip selects) emulation Up to 2 FlexCAN interface (2.0B Active) Up to 20 KB on-chip SRAM with ECC with 32 message buffers Fail-safe protection 1 safety port based on FlexCAN with 32 Programmable watchdog timer message buffers and up to 8 Mbit/s at Non-maskable interrupt 64 MHz capability usable as second CAN Fault collection unit when not used as safety port Nexus Class 1 interface One 10-bit analog-to-digital converter (ADC) Interrupts and events Up to 16 input channels (16 on LQFP100 / 12 on LQFP64) 16-channel eDMA controller Conversion time < 1 s including sampling 16 priority level controller time at full precision Up to 25 external interrupts Programmable Cross Triggering Unit (CTU) PIT implements four 32-bit timers 4 analog watchdogs with interrupt 120 interrupts are routed via INTC capability General purpose I/Os On-chip CAN/UART bootstrap loader with Boot Individually programmable as input, output Assist Module (BAM) or special function 1 FlexPWM unit: 8 complementary or 37 on LQFP64 independent outputs with ADC synchronization 64 on LQFP100 signals 1 general purpose eTimer unit 6 timers each with up/down capabilities Table 1. Device summary 16-bit resolution, cascadable counters Code flash memory Quadrature decode with rotation direction Package flag 192 KB 256 KB Double buffer input capture and output LQFP100 SPC560P34L3 SPC560P40L3 compare LQFP64 SPC560P34L1 SPC560P40L1 September 2013 Doc ID 16100 Rev 7 1/103 This is information on a product in full production. www.st.com 1Contents SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Contents 1 Introduction 7 1.1 Document overview 7 1.2 Description . 7 1.3 Device comparison . 7 1.4 Block diagram . 9 1.5 Feature details . 13 1.5.1 High performance e200z0 core processor . 13 1.5.2 Crossbar switch (XBAR) 13 1.5.3 Enhanced direct memory access (eDMA) . 14 1.5.4 Flash memory 14 1.5.5 Static random access memory (SRAM) . 15 1.5.6 Interrupt controller (INTC) . 16 1.5.7 System status and configuration module (SSCM) . 16 1.5.8 System clocks and clock generation . 17 1.5.9 Frequency-modulated phase-locked loop (FMPLL) 17 1.5.10 Main oscillator 17 1.5.11 Internal RC oscillator . 17 1.5.12 Periodic interrupt timer (PIT) . 18 1.5.13 System timer module (STM) . 18 1.5.14 Software watchdog timer (SWT) 18 1.5.15 Fault collection unit (FCU) . 18 1.5.16 System integration unit Lite (SIUL) . 19 1.5.17 Boot and censorship . 19 1.5.18 Error correction status module (ECSM) . 19 1.5.19 Peripheral bridge (PBRIDGE) 20 1.5.20 Controller area network (FlexCAN) 20 1.5.21 Safety port (FlexCAN) 21 1.5.22 Serial communication interface module (LINFlex) . 22 1.5.23 Deserial serial peripheral interface (DSPI) 23 1.5.24 Pulse width modulator (FlexPWM) 23 1.5.25 eTimer 25 1.5.26 Analog-to-digital converter (ADC) module . 25 1.5.27 Cross triggering unit (CTU) 26 1.5.28 Nexus Development Interface (NDI) . 26 2/103 Doc ID 16100 Rev 7