SPC560P44L3, SPC560P44L5 SPC560P50L3, SPC560P50L5 32-bit Power Architecture based MCU with 576 KB Flash memory and 40 KB SRAM for automotive chassis and safety applications Datasheet production data Features 64 MHz, single issue, 32-bit CPU core complex (e200z0h) Compliant with Power Architecture embedded category LQFP144 (20 x 20 x 1.4 mm) Variable Length Encoding (VLE) LQFP100 (14 x 14 x 1.4 mm) Memory organization 1 safety port based on FlexCAN with 32 message objects and up to 7.5 Mbit/s Up to 512 KB on-chip code flash memory capability usable as second CAN when not with ECC and erase/program controller used as safety port Additional 64 (4 16) KB on-chip data flash 1 FlexRay module (V2.1) with selectable memory with ECC for EEPROM emulation dual or single channel support, 32 Up to 40 KB on-chip SRAM with ECC message objects and up to 10 Mbit/s Fail safe protection (512 KB device only) Programmable watchdog timer Two 10-bit analog-to-digital converters (ADC) Non-maskable interrupt 2 11 input channels, + 4 shared channels Fault collection unit Conversion time < 1 s including sampling Nexus L2+ interface time at full precision Interrupts Programmable ADC Cross Triggering Unit (CTU) 16-channel eDMA controller 4 analog watchdogs with interrupt 16 priority level controller capability General purpose I/Os individually On-chip CAN/UART bootstrap loader with Boot programmable as input, output or special Assist Module (BAM) function 1 FlexPWM unit: 8 complementary or 2 general purpose eTimer units independent outputs with ADC synchronization 6 timers each with up/down count signals capabilities 16-bit resolution, cascadable counters Table 1. Device summary Quadrature decode with rotation direction Part number flag Package Double buffer input capture and output 448 KB Flash 576 KB Flash compare LQFP144 SPC560P44L5 SPC560P50L5 Communications interfaces LQFP100 SPC560P44L3 SPC560P50L3 2 LINFlex channels (LIN 2.1) 4 DSPI channels with automatic chip select generation 1 FlexCAN interface (2.0B Active) with 32 message objects September 2013 Doc ID 14723 Rev 9 1/112 This is information on a product in full production. www.st.com 1Contents SPC560P44Lx, SPC560P50Lx Contents 1 Introduction 7 1.1 Document overview 7 1.2 Description . 7 1.3 Device comparison . 7 1.4 Block diagram . 9 1.5 Feature details . 13 1.5.1 High performance e200z0 core processor . 13 1.5.2 Crossbar switch (XBAR) 13 1.5.3 Enhanced direct memory access (eDMA) . 14 1.5.4 Flash memory 14 1.5.5 Static random access memory (SRAM) . 15 1.5.6 Interrupt controller (INTC) . 15 1.5.7 System status and configuration module (SSCM) . 16 1.5.8 System clocks and clock generation . 16 1.5.9 Frequency-modulated phase-locked loop (FMPLL) 17 1.5.10 Main oscillator 17 1.5.11 Internal RC oscillator . 17 1.5.12 Periodic interrupt timer (PIT) . 17 1.5.13 System timer module (STM) . 18 1.5.14 Software watchdog timer (SWT) 18 1.5.15 Fault collection unit (FCU) . 18 1.5.16 System integration unit Lite (SIUL) . 18 1.5.17 Boot and censorship . 19 1.5.18 Error correction status module (ECSM) . 19 1.5.19 Peripheral bridge (PBRIDGE) 20 1.5.20 Controller area network (FlexCAN) 20 1.5.21 Safety port (FlexCAN) 21 1.5.22 FlexRay . 22 1.5.23 Serial communication interface module (LINFlex) . 22 1.5.24 Deserial serial peripheral interface (DSPI) 23 1.5.25 Pulse width modulator (FlexPWM) 23 1.5.26 eTimer 25 1.5.27 Analog-to-digital converter (ADC) module . 25 1.5.28 Cross triggering unit (CTU) 26 2/112 Doc ID 14723 Rev 9