SPC564A70L7CFAY STMicroelectronics

SPC564A70B4, SPC564A70L7 32-bit Power Architecture based MCU for automotive powertrain applications Datasheet preliminary data Features 150 MHz e200z4 Power Architecture core PBGA324 (23 mm x 23 mm) LQFP176 (24 mm x 24 mm) Variable length instruction encoding (VLE) 1 FlexRay module (V2.1) up to 10 Mbit/s Superscalar architecture with 2 execution w/dual or single channel, 128 message units objects, ECC Up to 2 integer or floating point instructions per cycle 1 eMIOS (24 unified channels) Up to 4 multiply and accumulate operations 1 eTPU2 (second generation eTPU) per cycle 32 standard channels Memory organization 1 reaction module (6 channels with 3 2 MB on-chip flash memory with ECC and outputs per channel) read-while-write (RWW) 2 enhanced queued analog-to-digital 128 KB on-chip SRAM with standby converters (eQADCs) functionality (32 KB) and ECC Forty 12-bit input channels 8 KB instruction cache (with line locking), 688 ns minimum conversion time configurable as 2- or 4-way On-chip CAN/SCI Bootstrap loader with Boot 14 + 3 KB eTPU code and data RAM Assist Module (BAM) 4 4 crossbar switch (XBAR) Nexus: Class 3+ for core Class 1 for eTPU 24-entry MMU JTAG (5-pin) Fail Safe Protection Development Trigger Semaphore (DTS) 16-entry Memory Protection Unit (MPU) Clock generation CRC unit with 3 submodules On-chip 440 MHz main oscillator Junction temperature sensor On-chip FMPLL (frequency-modulated Interrupt phase-locked loop) Configurable interrupt controller (INTC) Up to 112 general purpose I/O lines with non-maskable interrupt (NMI) 64-channel eDMA Power reduction modes: slow, stop, and standby Serial channels Flexible supply scheme 3 eSCI modules 5 V single supply with external ballast 3 DSPI modules (2 of which support downstream Micro Second Channel MSC ) Multiple external supply: 5 V, 3.3 V , and 1.2 V 3 FlexCAN modules with 64 message buffers each Designed for LQFP176, LBGA208, PBGA324 Table 1. Device summary Part number Memory Flash size Package LQFP176 Package LBGA208 Package PBGA324 2MB SPC564A70L7 - SPC564A70B4 September 2013 Doc ID 18078 Rev 4 1/133 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com 1 change without notice. Contents SPC564A70B4, SPC564A70L7 Contents 1 Introduction 8 1.1 Document overview 8 1.2 Description . 8 1.3 Device feature summary 8 1.4 Block diagram 10 1.5 Feature details . 15 1.5.1 e200z4 core 15 1.5.2 Crossbar switch (XBAR) 16 1.5.3 Enhanced direct memory access (eDMA) . 16 1.5.4 Interrupt controller (INTC) . 17 1.5.5 Memory protection unit (MPU) 17 1.5.6 Frequency-modulated phase-locked loop (FMPLL) 18 1.5.7 System integration unit (SIU) . 19 1.5.8 Flash memory 20 1.5.9 Static random access memory (SRAM) . 21 1.5.10 Boot assist module (BAM) . 21 1.5.11 Enhanced modular input/output system (eMIOS) . 21 1.5.12 Second generation enhanced time processing unit (eTPU2) 22 1.5.13 Reaction module (REACM) 24 1.5.14 Enhanced queued analog-to-digital converter (eQADC) 24 1.5.15 Deserial serial peripheral interface (DSPI) 26 1.5.16 Enhanced serial communications interface (eSCI) 27 1.5.17 Controller area network (FlexCAN) 27 1.5.18 FlexRay . 29 1.5.19 System timers 29 1.5.20 Software watchdog timer (SWT) 30 1.5.21 Cyclic redundancy check (CRC) module 30 1.5.22 Error correction status module (ECSM) . 30 1.5.23 Peripheral bridge (PBRIDGE) 31 1.5.24 Calibration bus interface 31 1.5.25 Power management controller (PMC) 31 1.5.26 Nexus port controller (NPC) 32 1.5.27 JTAG controller (JTAGC) 32 1.5.28 Development trigger semaphore (DTS) . 32 2/133 Doc ID 18078 Rev 4