SPC564A80L7CFAR STMicroelectronics

SPC564A74B4, SPC564A74L7, SPC564A80B4, SPC564A80L7 32-bit MCU family built on the embedded Power Architecture Features 150 MHz e200z4 Power Architecture core LBGA208 PBGA324 Variable length instruction encoding (VLE) LQFP176 Superscalar architecture with 2 execution 3 FlexCAN with 64 messages each units 1 FlexRay module (V2.1) up to 10 Mbit/s Up to 2 integer or floating point instructions with dual or single channel and 128 per cycle message objects and ECC Up to 4 multiply and accumulate operations 1 eMIOS per cycle 1 eTPU2 (second generation eTPU) Memory organization 2 enhanced queued analog-to-digital 4 MB on-chip flash memory with ECC and converters (eQADCs) Read While Write (RWW) On-chip CAN/SCI/FlexRay Bootstrap loader 192 KB on-chip RAM with standby with Boot Assist Module (BAM) functionality (32 KB) and ECC Nexus: Class 3+ for core Class 1 for the eTPU 8 KB instruction cache (with line locking), configurable as 2- or 4-way JTAG (5-pin) 14 + 3 KB eTPU code and data RAM Development Trigger Semaphore (DTS) 5 4 crossbar switch (XBAR) Clock generation 24-entry MMU On-chip 440 MHz main oscillator External Bus Interface (EBI) with slave and On-chip FMPLL (frequency-modulated master port phase-locked loop) Fail Safe Protection Up to 120 general purpose I/O lines 16-entry Memory Protection Unit (MPU) Power reduction mode: slow, stop and stand- CRC unit with 3 sub-modules by modes Junction temperature sensor Flexible supply scheme Interrupts 5 V single supply with external ballast Configurable interrupt controller (with NMI) Multiple external supply: 5 V, 3.3 V and 64-channel DMA 1.2 V Serial channels Designed for LQFP176, LBGA208, PBGA324 3 eSCI and Known Good Die (KGD) 3 DSPI (2 of which support downstream Micro Second Channel MSC ) Table 1. Device summary Part number Memory Flash size Package LQFP176 Package: LBGA208 Package: PBGA324 KGD 4MB SPC564A80L7 - SPC564A80B4 - 3MB SPC564A74L7 - SPC564A74B4 - September 2013 Doc ID 15399 Rev 9 1/157 www.st.com 1Contents SPC564A74L7, SPC564A80B4, SPC564A80L7 Contents 1 Introduction 8 1.1 Document Overview 8 1.2 Description . 8 1.3 Device comparison . 9 1.4 SPC564A80 feature list 11 1.5 Feature details . 13 1.5.1 e200z4 core 13 1.5.2 Crossbar Switch (XBAR) 13 1.5.3 eDMA . 14 1.5.4 Interrupt controller . 14 1.5.5 Memory protection unit (MPU) 15 1.5.6 FMPLL 16 1.5.7 SIU . 16 1.5.8 Flash memory 17 1.5.9 BAM 18 1.5.10 eMIOS 19 1.5.11 eTPU2 19 1.5.12 Reaction module 21 1.5.13 eQADC . 21 1.5.14 DSPI . 23 1.5.15 eSCI 24 1.5.16 FlexCAN . 24 1.5.17 FlexRay . 26 1.5.18 System timers 26 1.5.19 Software watchdog timer (SWT) 27 1.5.20 Cyclic redundancy check (CRC) module 27 1.5.21 Error correction status module (ECSM) . 27 1.5.22 External bus interface (EBI) 28 1.5.23 Calibration EBI 28 1.5.24 Power management controller (PMC) 29 1.5.25 Nexus port controller . 29 1.5.26 JTAG . 29 1.5.27 Development Trigger Semaphore (DTS) 29 1.6 SPC564A80 series architecture 30 2/157 Doc ID 15399 Rev 9