SPC56EL70L5CBFR STMicroelectronics

SPC56EL70L3, SPC56EL70L5, SPC564L70L3, SPC564L70L5 32-bit Power Architecture microcontroller for automotive SIL3/ASILD chassis and safety applications Datasheet - production data Replicated junction temperature sensor Non Maskable Interrupt (NMI) 16-region Memory Protection Unit (MPU) Clock Monitoring Units (CMU) Power Management Unit (PMU) Cyclic Redundancy Check (CRC) unit LQFP100 (14 x 14x 1.4 mm) LQFP144 (20 x 20 x 1.4 mm) Decoupled Parallel mode for high performance use of replicated cores Features Nexus Class 3+ interface Interrupts High-performance e200z4d dual core Replicated 16-priority controller 32-bit Power Architecture technology CPU Replicated 16-channel eDMA controller Core frequency as high as 120 MHz GPIOs individually programmable as input, Dual issue five-stage pipeline core output or special function Variable Length Encoding (VLE) Three 6-channel general-purpose eTimer units Memory Management Unit (MMU) 2 FlexPWM units: Four 16-bit channels per 4 KB instruction cache with error detection module code Communications interfaces Signal Processing Engine (SPE) 2 LINFlexD channels Memory available 3 DSPI channels with automatic chip select 2 MB flash memory with ECC generation 192 KB on-chip SRAM with ECC 3 FlexCAN interfaces (2.0B Active) with 32 Built-in RWW capabilities for EEPROM message objects emulation FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data SIL3/ASILD innovative safety concept: Lock rates up to 10 Mbit/s step mode and Fail-safe protection Sphere of Replication (SoR) for key Two 12-bit Analog-to-digital Converters (ADC) components (such as CPU core, eDMA, 16 input channels crossbar switch) Programmable Cross Triggering Unit (CTU) Fault Collection and Control Unit (FCCU) to synchronize ADCs conversion with timer Redundancy Control and Checker Unit and PWM (RCCU) on outputs of the SoR connected Sine wave generator (D/A with low pass filter) to FCCU On-chip CAN/UART/FlexRay Bootstrap loader Boot-time Built-In Self-Test for Memory Single 3.0 V to 3.6 V voltage supply (MBIST) and Logic (LBIST) triggered by hardware Ambient temperature range 40 C to 125 C Boot-time Built-In Self-Test for ADC and Junction temperature range 40 C to 150 C flash memory triggered by software Replicated safety enhanced watchdog July 2015 DocID023953 Rev 5 1/128 This is information on a product in full production. www.st.comContents SPC56EL70L3, SPC56EL70L5,PC564L70L3, SPC564L70L5 Contents 1 Introduction 7 1.1 Document overview 7 1.2 Description . 7 1.3 Device comparison . 8 1.4 Block diagram .11 1.5 Feature details . 12 1.5.1 High-performance e200z4d core 12 1.5.2 Crossbar switch (XBAR) 13 1.5.3 Memory protection unit (MPU) 13 1.5.4 Enhanced direct memory access (eDMA) . 13 1.5.5 On-chip flash memory with ECC 14 1.5.6 On-chip SRAM with ECC 14 1.5.7 Platform flash memory controller 15 1.5.8 Platform static RAM controller (SRAMC) 15 1.5.9 Memory subsystem access time 16 1.5.10 Error correction status module (ECSM) . 16 1.5.11 Peripheral bridge (PBRIDGE) 17 1.5.12 Interrupt controller (INTC) . 17 1.5.13 System clocks and clock generation . 18 1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL) 18 1.5.15 Main oscillator 19 1.5.16 Internal reference clock (RC) oscillator . 19 1.5.17 Clock, reset, power, mode and test control modules (MC CGM, MC RGM, MC PCU, and MC ME) . 19 1.5.18 Periodic interrupt timer module (PIT) . 19 1.5.19 System timer module (STM) . 20 1.5.20 Software watchdog timer (SWT) 20 1.5.21 Fault collection and control unit (FCCU) 20 1.5.22 System Integration Unit Lite (SIUL) 20 1.5.23 Non-maskable interrupt (NMI) 21 1.5.24 Boot assist module (BAM) . 21 1.5.25 System status and configuration module (SSCM) . 21 1.5.26 FlexCAN 21 1.5.27 FlexRay . 23 2/128 DocID023953 Rev 5