SPC574S64E3CEFAR STMicroelectronics

SPC574S60E3, SPC574S64E3 32-bit Power Architecture microcontroller for automotive ASILD applications Datasheet - production data Cyclic redundancy check (CRC) unit 8 enhanced 12-bit SAR analog converters 2 sets of: 3 ADCs and one supervisor ADC eTQFP100 (14 x 14 x 1.0 mm) 1.5 s conversion time at 12 MHz Up to 32 physical channels Features Dual Programmable CTU 4 general purpose eTimer units (6 channels AEC-Q100 qualified each) High performance e200z4d dual core 4 FlexPWM units 32-bit Power Architecture technology CPU 2 (4 channels each) used for motor control Core frequency as high as 140 MHz with hardware synchronization between the Dual issue 5-stage pipeline in-order control systems execution core 2 (2 channels each) used for SWG Variable Length Encoding (VLE) emulation Core MPU Communication interfaces Floating Point, End-to-End Error Correction 4 LINFlexD modules 8 KB instruction cache with error detection 4 deserial serial peripheral interface (DSPI) code modules 32 KB local data RAM and 4 KB data cache 2 MCAN interfaces with advanced shared along with 8 KB instruction cache memory scheme (808 x 32-bit words for 1600 KB (1.5 MB code + 64 KB data) on-chip MCAN0 and 520 x 32-bit words for flash memory: supports read during program MCAN1) and CAN-FD support and erase operations, and multiple blocks 1 FlexRay module with 2 channels, 128 allowing EEPROM emulation message buffers 128 KB on-chip RAM (96 KB on chip 2 SENT interfaces (3 channels each) RAM + 32 KB local data RAM) Dual phase-locked loops with stable clock Multi-channel direct memory access controller domain for peripherals and FM modulation (eDMA) with 32 channels domain for computational shell Comprehensive new generation ASILD safety Nexus Class 3 debug and trace interface concept On-chip CAN/UART Bootstrap loader with ASILD SEooC approach (Safety Element BAF. Physical Interface (PHY) can be UART out of Context) Advanced and flexible supply scheme FCCU for collection and reaction to failure On-chip voltage regulator for 1.2 V core notifications logic supply. Bypass mode supported for Memory Error Management Unit (MEMU) external 1.2 V core logic supply for collection and reporting of error events 3.3 V or 5 V IO and ADC supply (2 in memories independent power domains available) End-to-end Error Correction Code Junction temperature range -40 C to 150 C (e2eECC) logic February 2020 DS10601 Rev 6 1/77 This is information on a product in full production. www.st.comContents SPC574Sx Contents 1 Introduction 4 1.1 Document overview 4 1.2 Description . 4 1.3 Feature overview 7 1.4 Block diagram . 9 2 Package pinouts and signal descriptions . 13 2.1 Package pinouts 13 2.2 Pin descriptions 14 2.3 Package pads/pins 14 3 Electrical characteristics 20 3.1 Introduction . 20 3.2 Parameter classification 20 3.3 Absolute maximum ratings 21 3.4 Electromagnetic compatibility (EMC) 22 3.5 Electrostatic discharge (ESD) . 22 3.6 Operating conditions 22 3.7 Thermal characteristics 25 3.7.1 Package thermal characteristics 25 3.7.2 Power considerations 26 3.8 Current consumption 28 3.9 I/O pad electrical characteristics . 29 3.9.1 I/O pad types . 29 3.9.2 I/O input DC characteristics 29 3.9.3 I/O output DC characteristics . 32 3.10 RESET electrical characteristics . 35 3.11 Power management . 38 3.11.1 Overview 38 3.11.2 Voltage regulator electrical characteristics 39 3.11.3 Power Schemes . 41 3.11.4 Decoupling capacitors 44 2/77 DS10601 Rev 6