SPC58EC80E7QMC0Y STMicroelectronics

SPC584Cx, SPC58ECx SPC58 C Line - 32 bit Power Architecture automotive MCU Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B Datasheet - production data Memory Error Management Unit (MEMU) for collection and reporting of error events in memories Cyclic redundancy check (CRC) unit eTQFP64 (10 x 10 x 1.0 mm) eTQFP100 (14 x 14 x 1.0 mm) Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Body cross triggering unit (BCTU) eTQFP144 (20 x 20 x 1.0 mm) eLQFP176 (24 x 24 x 1.4 mm) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT RTIs FPBGA292 (17 x 17 x 1.8 mm) Enhanced modular IO subsystem (eMIOS): up to 64 timed I/O channels with 16-bit counter resolution Features Enhanced analog-to-digital converter system AEC-Q100 qualified with: High performance e200z420n3 dual core 3 independent fast 12-bit SAR analog converters 32-bit Power Architecture technology CPU 1 supervisor 12-bit SAR analog converter Core frequency as high as 180 MHz 1 10-bit SAR analog converter with STDBY Variable Length Encoding (VLE) mode support 4224 KB (4096 KB code flash + 128 KB data Communication interfaces flash) on-chip flash memory: supports read during program and erase operations, and 18 LINFlexD modules multiple blocks allowing EEPROM emulation 8 deserial serial peripheral interface (DSPI) modules 176 KB HSM dedicated flash memory (144 KB code + 32 KB data) 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support 384 KB on-chip general-purpose SRAM (in Dual-channel FlexRay controller addition to 128 KB core local data RAM: 64 KB included in each CPU) 1 ethernet controller 10/100 Mbps, compliant IEEE 802.3-2008 Multi-channel direct memory access controller (eDMA) with 64 channels Low power capabilities Versatile low power modes 1 interrupt controller (INTC) Ultra low power standby with RTC Comprehensive new generation ASIL-B safety Smart Wake-up Unit for contact monitoring concept Fast wakeup schemes ASIL-B of ISO 26262 FCCU for collection and reaction to failure Dual phase-locked loops with stable clock notifications domain for peripherals and FM modulation domain for computational shell May 2021 DS11620 Rev 8 1/153 This is information on a product in full production. www.st.comSPC584Cx, SPC58ECx Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART Junction temperature range -40 C to 150 C Table 1. Device summary Part number Package 2 MB 3 MB 4 MB Single core Dual core Single core Dual core Single core Dual core eTQFP64 SPC584C70E1 SPC58EC70E1 SPC584C74E1 SPC58EC74E1 SPC584C80E1 SPC58EC80E1 eTQFP100 SPC584C70E3 SPC58EC70E3 SPC584C74E3 SPC58EC74E3 SPC584C80E3 SPC58EC80E3 eTQFP144 SPC584C70E5 SPC58EC70E5 SPC584C74E5 SPC58EC74E5 SPC584C80E5 SPC58EC80E5 eLQFP176 SPC584C70E7 SPC58EC70E7 SPC584C74E7 SPC58EC74E7 SPC584C80E7 SPC58EC80E7 FPBGA292 SPC584C70C3 SPC58EC70C3 SPC584C74C3 SPC58EC74C3 SPC584C80C3 SPC58EC80C3 2/153 DS11620 Rev 8