SPC58EE84E7QMSAR STMicroelectronics

SPC58EEx, SPC58NEx 32-bit Power Architecture microcontroller for automotive ASIL-D applications Datasheet - production data Junction temperature range -40 C to 165 C GTM 343 - Generic Timer Module: Intelligent complex timer module FPBGA292 (17 x 17 x 1.8 mm) 144 channels (40 input and 104 output) eLQFP176 (24 x 24 x 1.4 mm) 5 programmable fine grain multi-threaded cores Known Good Die 24-bit wide channels Enhanced analog-to-digital converter system Features with: 1 supervisor 12-bit SAR analog converter AEC-Q100 qualified 4 separate fast 12-bit SAR analog 32-bit Power Architecture VLE compliant CPU converters cores: 3 separate 10-bit SAR analog converters, Three main CPUs, dual issue, 32-bit CPU one with STDBY mode support core complexes (e200z4), two of them 6 separate 16-bit Sigma-Delta analog having one checker core in lock-step converters Floating Point, End-to-End Error Correction Communication interfaces: 6576 KB (6288 KB code flash + 288 KB data 18 LINFlexD modules flash) on-chip flash memory: 10 deserial serial peripheral interface supports read during program and erase (DSPI) modules operations, and multiple blocks allowing 8 MCAN interfaces with advanced shared EEPROM emulation memory scheme and ISO CAN-FD support, Supports read while read between the two one supporting time-triggered controller code Flash partitions. area network (TTCAN) 608 KB on-chip general-purpose SRAM (in Two Ethernet controller 10/100 Mbps, addition to 160 KB core local data RAM) compliant IEEE 802.3-2008 96-channel direct memory access controller Flexible Power Supply options: (eDMA) External Regulators (1.2 V core, 3.3 V5 V Comprehensive new generation ASIL-D safety IO) concept: Single internal SMPS regulator ASIL-D of ISO 26262 (eLQFP176) FCCU for collection and reaction to failure Single internal Linear Regulator with notifications external ballast (FPBGA292) Memory Error Management Unit (MEMU) Nexus development interface (NDI) per IEEE- for collection and reporting of error events ISTO 5001-2003 standard, with some support in memories for 2010 standard Cyclic redundancy check (CRC) unit Boot assist Flash (BAF) supports factory Dual-channel FlexRay controller programming using a serial bootload through Hardware Security Module (HSM) the asynchronous CAN or LIN/UART July 2019 DS11646 Rev 4 1/154 This is information on a product in full production. www.st.comSPC58EEx, SPC58NEx Table 1. Device summary Part number Package 4MB 6 MB Dual core Triple core Dual core Triple core eLQFP176 SPC58EE80E7 SPC58NE80E7 SPC58EE84E7 SPC58NE84E7 FPBGA292 SPC58EE80C3 SPC58NE80C3 SPC58EE84C3 SPC58NE84C3 KGD SPC58NE84H0 2/154 DS11646 Rev 4