SPC584Gx, SPC58EGx, SPC58NGx 32-bit Power Architecture microcontroller for automotive ASIL-D applications Datasheet - production data Logic BIST FCCU for collection and reaction to failure notifications Memory BIST eTQFP144 (20 x 20 x 1.0 mm) eLQFP176 (24 x 24 x 1.4 mm) Cyclic redundancy check (CRC) unit Memory Error Management Unit (MEMU) for collection and reporting of error events FPBGA292 (17 x 17 x 1.8 mm) in memories Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from Features multiple bus masters with end-to-end ECC AEC-Q100 qualified Body cross triggering unit (BCTU) High performance e200z4 triple core: Triggers ADC conversions from any eMIOS 32-bit Power Architecture technology CPU channel Core frequency as high as 180 MHz Triggers ADC conversions from up to 2 dedicated PIT RTIs Variable Length Encoding (VLE) Floating Point, End-to-End Error Correction Enhanced modular IO subsystem (eMIOS): up to 64 timed IO channels with 16-bit counter 6582 KB (6144 KB code flash+ 256 KB data resolution flash) on-chip flash memory: Enhanced analog-to-digital converter system supports read during program and erase with: operations, and multiple blocks allowing EEPROM emulation 4 independent fast 12-bit SAR analog converters Supports read while read between the two code Flash partitions. One supervisor 12-bit SAR analog converter 608 KB on-chip general-purpose SRAM (in One standby 10-bit SAR analog converter addition to 160 KB core local data RAM): 64KB in CPU 0, 64 KB in CPU 1 and 32 KB in Communication interfaces: CPU 2 18 LINFlexD modules 182 KB HSM dedicated flash memory (144 KB 10 deserial serial peripheral interface code + 32 KB data) (DSPI) modules Multi-channel direct memory access controller 8 MCAN interfaces with advanced shared (eDMA) memory scheme and ISO CAN-FD support one eDMA with 64 channels Dual-channel FlexRay controller one eDMA with 32 channels Two independent Ethernet controllers 10/100Mbps compliant IEEE 802.3-2008 1 interrupt controller (INTC) Low power capabilities Comprehensive new generation ASIL-D safety Versatile low power modes concept: Ultra low power standby with RTC ASIL-D of ISO 26262 Smart Wake-up Unit for contact monitoring One CPU channel in lockstep July 2019 DS11758 Rev 6 1/139 This is information on a product in full production. www.st.comSPC584Gx, SPC58EGx and SPC58NGx Fast wakeup schemes Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some support for 2010 standard Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART Junction temperature range -40 C to 150 C Table 1. Device summary Part number Package 4 MB 6 MB Single core Dual core Triple core Single core Dual core Triple core eTQFP144 SPC584G80E5 SPC58EG80E5 SPC58NG80E5 SPC584G84E5 SPC58EG84E5 SPC58NG84E5 eLQFP176 SPC584G80E7 SPC58EG80E7 SPC58NG80E7 SPC584G84E7 SPC58EG84E7 SPC58NG84E7 FPBGA292 SPC584G80C3 SPC58EG80C3 SPC58NG80C3 SPC584G84C3 SPC58EG84C3 SPC58NG84C3 2/139 DS11758 Rev 6