SPEAR300-2 STMicroelectronics

SPEAr300 Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface Features ARM926EJ-S core up to 333 MHz High-performance 8-channel DMA Dynamic power-saving features Configurable peripheral functions on 102 LFBGA289 (15 x 15 x 1.7 mm) shared I/Os (please refer to Table 11: PL GPIO multiplexing scheme) Touchscreen support (using the ADC) Memory 9 x 9 keyboard controller 32 KB ROM and 56 KB internal SRAM Glueless management of up to 8 LPDDR-333/DDR2-666 external memory SLICs/CODECs interface (up to 1 GB addressable memory) Miscellaneous functions SDIO/MMC card interface Integrated real time clock, watchdog, and Serial Flash memory interface (SMI) system controller Flexible static memory controller (FSMC) 8-channel 10-bit ADC, 1 Msps up to 16-bit data bus width, supporting 1-bit DAC external SRAM, NAND/NOR Flash and JPEG codec accelerator FPGAs Six 16-bit general purpose timers with Serial SPI Flash interface capture mode and programmable prescaler Connectivity Up to 62 GPIOs 2 x USB 2.0 Host USB 2.0 Device Applications Fast Ethernet (MII port) SPEAr300 embedded MPU is configurable in 1x SSP Synchronous serial peripheral 13 sets of peripheral functions targeting a (SPI, Microwire or TI protocol) range of applications: 2 1x I C General purpose NAND Flash or NOR 2 1x I S, Flash based devices 1x fast IrDA interface Digital photo frames 1x UART interface WiFi or IP phones (low end or high end) TDM bus (512 timeslots) 2 ATA PABX systems (with or without I S) 2 Up to 8 additional I C/SPI chip selects 8-bit or 14-bit camera (with or without LCD) Security C3 cryptographic accelerator Table 1. Device summary Peripherals supported Temp Order code Package Packing Camera interface (ITU-601/656 and CSI2 range, C support) LFBGA289 TFT/STN LCD controller (resolution up to SPEAR300-2 - 40 to 85 C (15x15 mm) Tray 1024 x 768 and up to 24 bpp) pitch 0.8 mm April 2010 Doc ID 16324 Rev 2 1/83 www.st.com 1Contents SPEAr300 Contents 1 Description . 8 1.1 Main features: . 9 2 Architecture overview . 11 2.1 ARM926EJ-S CPU 11 2.2 System controller . 12 2.2.1 Clock and reset system . 12 2.2.2 Power saving system mode control 13 2.3 Vectored interrupt controller (VIC) 14 2.4 General purpose timers 14 2.5 Watchdog timer 14 2.6 RTC oscillator 15 2.7 Multichannel DMA controller 15 2.8 Embedded memory units . 15 2.9 Mobile DDR/DDR2 memory controller . 15 2.10 Serial memory interface 15 2.11 Flexible static memory controller (FSMC) 17 2.12 UART 17 2.13 Fast IrDA controller (FIrDA) . 17 2.14 Synchronous serial port (SSP) . 18 2.15 I2C 19 2.16 SPI I2C multiple slave control . 20 2.17 TDM interface 20 2 2.18 I S interface . 21 2.19 GPIOs . 21 2.20 Keyboard controller . 22 2.21 CLCD controller 22 2.22 Camera interface . 23 2.23 SDIO controller/MMC card interface 24 2.24 Ethernet controller 25 2.25 USB2 host controller 25 2/83 Doc ID 16324 Rev 2