ST10F280 STMicroelectronics

ST10F280 16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM Datasheet production data Features High performance cpu with dsp functions 16-bit CPU with 4-stage pipeline. 50ns Instruction cycle time at 40MHz CPU clock PBGA208 (23 x 23 x 1.96 - Pitch 1.27 mm) Multiply/accumulate unit (MAC) 16 x 16-bit (Plastic Bold Grid Array) multiplication, 40-bit accumulator ORDER CODE: ST10F280-JT3 Repeat unit A/D converter Enhanced boolean bit manipulation 2X16-channel 10-bit facilities 4.85s conversion time Additional instructions to support hll and operating systems One timer for adc channel injection Single-cycle context switching support 8-channel PWM unit Memory organization Serial channels 512KB on-chip Flash memory single Synchronous/async serial channel voltage with erase/program controller High-speed synchronous channel 100K erasing/programming cycles Fail-safe protection 20 year data retention time Programmable watchdog timer Up to 16MB linear address space for code Oscillator watchdog and data (5MB with CAN) Two CAN 2.0b interfaces operating on one or 2KB on-chip internal ram (IRAM) two can busses (30 or 2x15 message objects) 16KB extension RAM (XRAM) On-chip bootstrap loader Fast and flexible bus Clock generation Programmable external bus characteristics for different address ranges On-chip PLL 8-bit or 16-bit external data bus Direct or prescaled clock input Multiplexed or demultiplexed external Up to 143 general purpose i/o lines address/data buses Individually programmable as input, output Five programmable chip-select signals or special function Hold-acknowledge bus arbitration support Programmable threshold (hysteresis) Interrupt Idle and power down modes 8-channel peripheral event controller for Maximum cpu frequency 40MHz single cycle, interrupt driven data transfer Package PBGA 208 balls (23 x 23 x 1.96 mm - 16-priority-level interrupt system with 56 pitch 1.27 mm) sources, sample-rate down to 25ns Single voltage supply: 5 V 10% (embedded Two multi-functional general purpose timer regulator for 3.3 V core supply) units with 5 timers Temperature range: -40C to 125C Two 16-channel capture/compare units September 2013 Doc ID 8673 Rev 4 1/239 This is information on a product in full production. www.st.com 1Contents ST10F280 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Ball data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1 Visibility of XBUS peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Operational overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.2 Instructions and commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.3 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.4 Erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.5 Erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.6 In-system programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.7 Read/write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.8 Power supply, reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 Architectural description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 Command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.3 Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3.4 Flash Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.5 Instructions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.6 Reset processing and initial State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4 Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5.1 Handling of Flash addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5.2 Basic Flash access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.3 Programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6.1 Entering the bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2/239 Doc ID 8673 Rev 4