ST8500TR STMicroelectronics

ST8500 Programmable power line communication modem System on Chip Datasheet - production data 1 flexible CRC calculation unit 2 2 USART, 1 UART, 3 SPI, 1 I C Cryptographic engine AES 128/192/256 engine True random number generator Pseudo random number generator QFN56 (7 x 7 x 1 mm) Clock management: 25 MHz external crystal for system clock Integrated 25 MHz oscillator (XOSC) with Features frequency synthesizer (FS) and pre-scaler units to generate internal clock signals Programmable power line communication (PLC) modem System on Chip Power management Integrated differential PLC analog front-end 3.3 V external supply voltage for I/O and analog PGA with automatic gain control and ADC 2.5 V internal linear regulator for analog DAC with transmission pre-driver 1.1 V external supply voltage for digital Digital transmission level control Normal, Slow, Doze and low power modes Zero crossing comparator Up to 500 kHz PLC signal bandwidth Available in QFN56 package High performance, fully programmable real- -40 C to +105 C temperature range time engine dedicated to PLC PHY and real - time MAC protocol management (400 MHz Applications max. frequency) Dedicated code and data SRAM memories Smart metering, smart grid and Internet of Things applications Standard ARM 32-bit Cortex -M4F fully programmable core for protocol upper layers Suitable for application design compliant with and peripherals management CENELEC, FCC and ARIB regulations 200 MHz maximum frequency Table 1. Device summary 256 kB of embedded SRAM for code and data Order code Package Packing 96 kB of embedded SRAM for data ST8500 Tray 8 kB of embedded shared RAM QFN56 ST8500TR Tape and reel Bootloader ROM memory One Time Programmable (OTP) memory with dedicated areas available for secure keys and user information storage Serial wire and JTAG interfaces 24 multiplexed GPIOs 4 general purpose timers June 2018 DocID031029 Rev 3 1/37 This is information on a product in full production. www.st.comContents ST8500 Contents 1 Description . 4 2 Device architecture 5 2.1 Power line communication (PLC) subsystem . 6 2.1.1 Digital front-end (DFE) . 7 2.1.2 Analog front-end (AFE) 7 2.1.3 Real-time engine (RTE) 7 2.2 Protocol core subsystem 8 2.2.1 ARM Cortex-M4F core 8 2.2.2 Multi-AHB bus matrix 8 2.2.3 Debug with serial wire JTAG debug port (SWJ-DP) 9 2.2.4 Floating point unit (FPU) . 9 2.2.5 Nested vectored interrupt controller (NVIC) . 9 2.2.6 General-purpose input/outputs (GPIOs) 11 2.2.7 General-purpose timer (GPT) 11 2.2.8 Window Watchdog (WWDG) . 11 2.2.9 SysTick timer . 11 2.2.10 Universal synchronous/asynchronous receiver transmitters (USART) 11 2.2.11 Serial peripheral interface (SPI) . 12 2 2.2.12 Inter-integrated circuit interface (I C) . 12 2.2.13 AES engine 12 2.2.14 True random number generator (TRNG) 12 2.2.15 Pseudo random number generator (PRNG) . 13 2.2.16 CRC (cyclic redundancy check) calculation unit 13 2.3 Inter-processor communication (IPC) 13 2.4 Cortex memories . 13 2.4.1 Embedded SRAM (instruction and data) 13 2.4.2 Embedded SRAM (data only) 13 2.4.3 Embedded ROM 13 2.4.4 One Time Programmable (OTP) section 14 2.5 Clock and reset management (CRM) 15 2.5.1 Clock management 15 2.5.2 Reset management 16 2/37 DocID031029 Rev 3