STA120 DIGITAL AUDIO INTERFACE RECEIVER MONOLITHIC CMOS RECEIVER 3.3V SUPPLY VOLTAGE LOW-JITTER, ON-CHIP CLOCK RECOVERY 256xFs OUTPUT CLOCK PROVIDED SUPPORTS: AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 PROFESSIONAL AND CONSUMER FORMATS SO28 EXTENSIVE ERROR REPORTING REPEAT ORDERING NUMBER: STA120D LAST SAMPLE ON ERROR OPTION tion signals and de-multiplexes the audio and dig- DESCRIPTION ital data. Differential or single ended inputs can be The STA120 is a monolithic CMOS device that re- decoded. ceives and decodes audio data according to the The STA120 de-multiplexes the channel, user and AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 validity data directly to serial output pins with ded- interface standards. icated output pins for the most important channel The STA120 recovers the clock and synchroniza- status bits. BLOCK DIAGRAM VD+ DGND VA+ FILT AGND MCK M3 M2 M1 M0 22 20 21 19 17 18 24 23 7 8 26 SDATA 12 AUDIO 9 SCK SERIAL PORT RXP 11 CLOCK & DATA FSYNC RS422 RECOVERY Receiver 10 DE MUX RXN 1 C 14 REGISTERS U 28 MUX MUX VREF 13 16 6 5 4 3 2 27 25 15 D97AU613A CS12/FCK SEL C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2 ERF CBL December 2002 1/15STA120 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V , V Power Supply Voltage 4 V D+ A+ V Input Voltage ( excluding pins 9, 10) -0.3 to V + +0.3 V IN D T Ambient Operating Temperature (power applied) -30 to +85 C amb T Storage Temperature -40 to 150 C stg PIN CONNECTIONS (Top view) C 1 28 VERF Cd/F1 2 27 Ce/F2 Cc/F0 3 26 SDATA Cb/E2 4 25 ERF Ca/E1 5 24 M1 C0/E0 6 23 M0 VD+ 7 22 VA+ DGND 8 21 AGND RXP 9 20 FILT RXN 10 19 MCK FSYNC 11 18 M2 SCK 12 17 M3 CS12/FCK 13 16 SEL U 14 15 CBL D97AU609A PINS DESCRIPTION N. Name Description Power Supply 7V Positive Digital Power.Positive supply for the digital section. Nominally 3.3V. D+ 8 DGND Digital Ground.Ground for the digital section. 21 AGND Analog Ground.Ground for the analog section. AGND should be connected to same ground as DGND. 22 V Positive Analog Power.Positive supply for the analog section. Nominally 3.3V. A+ Audio Output Interface 11 FSYNC Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and may be an input or output. The format is based on M0, M1, M2 and M3 pins. 12 SCK Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3 pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must be provided in all normal modes. 17, 18, M2, M3, Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect 23, 24 M1, M0 to SDATA. 26 SDATA Serial Data. Audio data serial output pin. 2/15