STA333BW13TR STMicroelectronics

STA333BW 2.1 channel 40 W high-efficiency digital audio system Sound Terminal Datasheet - production data Dynamic range compression (DRC) or anticlipping mode Audio presets: 15 preset crossover filters 5 preset anticlipping modes Preset night-time listening mode Individual channel soft/hard mute Independent channel volume and DSP bypass PowerSSO-36 IS input data interface with exposed pad down (EPD) Input and output channel mapping Automatic invalid input-detect mute Up to 5 user-programmable biquads/channel Three coefficients banks for EQ presets storing Features with fast recall via IC interface Wide-range supply voltage, 4.5 V to 21.5 V Bass/treble tones and de-emphasis control Three power output configurations: Selectable high-pass filter for DC blocking 2 channels of ternary PWM (2 x 20 W into Advanced AM interference frequency 8 at 18 V) + PWM output switching and noise suppression modes 2 channels of ternary PWM (2 x 20 W into Sub channel mix into left and right channels 8 at 18 V) + ternary stereo line-out 2.1 channels of binary PWM (left, right, Selectable high- or low-bandwidth LFE) (2 x 9 W into 4 +1 x 20 W into 8 noise-shaping topologies at 18 V) Selectable clock input ratio FFX with 100-dB SNR and dynamic range 96 kHz internal processing sample rate Scalable FFX modulation index Thermal overload and short-circuit protection Selectable 32- to 192-kHz input sample rates technology IC control with selectable device address Video apps: 576 x f input mode supported S Digital gain/attenuation +48dB to -80dB with Pin and SW compatible with STA335BW, 0.5-dB/step resolution STA339BW, STA339BWS, STA559BW and STA559BWS Soft volume update with programmable ratio Individual channel and master gain/attenuation Table 1. Device summary Order code Package Packaging STA333BW13TR PowerSSO-36 EPD Tape and reel February 2014 DocID13773 Rev 5 1/68 This is information on a product in full production. www.st.comContents STA333BW Contents 1 Description . 8 2 Pin connections . 9 2.1 Connection diagram 9 2.2 Pin description 9 3 Electrical specifications . 11 3.1 Absolute maximum ratings .11 3.2 Thermal data .11 3.3 Recommended operating conditions 12 3.4 Electrical specifications for the digital section . 12 3.5 Electrical specifications for the power section . 13 3.6 Power-on/off sequence 15 4 Serial audio interface . 16 4.0.1 Timings . 16 4.0.2 Delay serial clock enable 16 4.0.3 Channel input mapping . 16 5 Processing data paths 17 6 IC bus specification 19 6.1 Communication protocol 19 6.1.1 Data transition or change 19 6.1.2 Start condition 19 6.1.3 Stop condition 19 6.1.4 Data input . 19 6.2 Device addressing 19 6.3 Write operation . 20 6.3.1 Byte write 20 6.3.2 Multi-byte write 20 6.4 Read operation . 20 6.4.1 Current address byte read . 20 2/68 DocID13773 Rev 5