STA559BW

STA559BW 5 V, 2 A, 2.1 channel high-efficiency digital audio system Sound Terminal Datasheet - production data Audio presets: 15 preset crossover filters 5 preset anti-clipping modes Preset night-time listening mode Individual channel soft/hard mute Independent channel volume and DSP bypass PowerSSO-36 2-channel IS input data interface with exposed pad down (EPD) Input and output channel mapping Automatic invalid-input detect Mute Automatic zero-detect mute Up to 4 user-programmable biquads/channel Features Three coefficients banks for EQ presets storing Wide-range supply voltage, 4.5 V to 16 V with fast recall via IC interface Three power output configurations: Bass/treble tones and de-emphasis control 2 channels of ternary PWM (2 x 3 W into Selectable high-pass filter for DC blocking 4 at 5 V) + PWM output Advanced AM interference frequency 2 channels of ternary PWM (2 x 3 W into switching and noise suppression modes 4 at 5 V) + ternary stereo line-out 2.1 channels of binary PWM (left, right, Selectable high- or low-bandwidth LFE) (2 x 0.7 W + 1 x 3 W into 4 at 5 V) noise-shaping topologies (2 x 1.4 W + 1 x 6 W into 2 at 5 V) Selectable clock input ratio FFX with 100-dB SNR and dynamic range Thermal overload and short-circuit protection Selectable 32- to 192-kHz input sample rates embedded IC control with selectable device address Video apps: 576 x f input mode supported S Digital gain/attenuation +48dB to -80dB with 0.5-dB/step resolution Soft volume update Table 1. Device summary Individual channel and master gain/attenuation Order code Package Packaging Two independent limiters/compressors STA559BWTR PowerSSO-36 EPD Tape and reel Dynamic range compression or anti-clipping modes February 2014 DocID18190 Rev 2 1/67 This is information on a product in full production. www.st.comContents STA559BW Contents 1 Description . 8 2 Pin connections . 9 2.1 Connection diagram 9 2.2 Pin description 9 3 Electrical specifications . 11 3.1 Absolute maximum ratings .11 3.2 Thermal data .11 3.3 Recommended operating conditions 12 3.4 Electrical specifications for the digital section . 12 3.5 Electrical specifications for the power section . 13 3.6 Power on/off sequence . 15 4 Processing data paths 16 5 IC bus specification 18 5.1 Communication protocol 18 5.1.1 Data transition or change 18 5.1.2 Start condition 18 5.1.3 Stop condition 18 5.1.4 Data input . 18 5.2 Device addressing 18 5.3 Write operation . 19 5.3.1 Byte write 19 5.3.2 Multi-byte write 19 5.4 Read operation . 19 5.4.1 Current address byte read . 19 5.4.2 Current address multi-byte read 19 5.4.3 Random address byte read 19 5.4.4 Random address multi-byte read 20 6 Register description 21 2/67 DocID18190 Rev 2