STA680Q STMicroelectronics

STA680 Automotive HD Radio baseband receiver Datasheet - production data Optional Serial Flash memory SPI interface for application code storage IIS serial audio interface with programmable sample rate converter Primary and secondary serial interfaces for 0 03 host micro communication based on industry LFBGA168 TFBGA289 standard IIC and SPI Several General purpose IOs One Internal clock oscillator and two internal PLLs Features External clock input AEC-Q100 qualified 1.2 V core supply 3.3 V I/O supply IBOC (in-band on-channel) digital audio broadcast signal decoding for AM/FM hybrid Description and all-digital modes The STA680 is an HD-radio base-band processor Dual-channel HD 1.5 for background scanning for car-radio applications. The STA680 and data services functionality includes audio decompression and HD codec (HDC) audio decompression data processing, while multiple interfaces ensure Metadata support for HD Radio reception flexible integration into the system. MPS (main program service), SPS The STA680 takes full advantage of HD 1.5 Radio (supplemental program service) and PAD benefits including CD-like audio quality from HD (program associated data) data decoding Radio FM broadcasts and FM-like audio quality Advanced HD Radio feature support: using HD Radio AM, while program associated data or traffic information is received from the Apple ID3 tag second channel. Multicasting Electronic program guide (EPG) STA680 supports FM/AM analog/digital AAA algorithm by mean of specific FW. Real-time traffic Automatic Audio Alignment (AAA) algorithm Table 1. Device summary support (1) Order code Package Packing Variable input base-band data-rate I2S-like interface supporting 650, 675, 744.1875, STA680 Tray LFBGA 168 balls 912 kS/s data rates (12x12x1.4 mm) STA680TR Tape & Reel Secondary RF base-band interface for dual STA680D Tray tuner applications TFBGA 289 balls (15x15x1.2 mm) STA680DTR Tape & Reel Glueless interface to Synchronous SDRAM addressing up to 512 Mbit of SDRAM in x16 1. ECOPACK compliant. configuration March 2019 DS5877 Rev 13 1/48 This is information on a product in full production. www.st.com 0 03 Contents STA680 Contents 1 Block diagram and pin description . 6 1.1 Block diagram . 6 1.2 Ball-out description . 6 1.2.1 LFBGA description 7 1.2.2 TFBGA description 8 1.2.3 Ball-out list 9 1.2.4 I/Os supply groups . 19 2 General description . 20 2.1 Receiver system overview 21 2.2 HD Radio processing 21 2.3 Dual channel HD 1.5 Radio processing 22 2.4 Overview of main functional blocks . 22 2.4.1 Adjacent channel filter 22 2.4.2 HiFi2 core . 22 2.4.3 Vectra core . 22 2.4.4 DMA 22 2.4.5 Hardware accelerator (VITERBI) 22 3 Operation and general remarks . 23 3.1 Clock schemes . 23 3.2 Power on . 25 4 Power supply ramp-up phase 26 4.1 Oscillator setting time 26 4.2 Boot sequence . 26 4.3 Normal operation mode 27 5 Digital I/O and memory interfaces . 28 5.1 Interfaces: LFBGA vs. TFBGA . 28 2 5.2 Base-band I S interface 29 2 5.3 Base-band I S interface frequency diversity 30 5.4 Audio interface (AIF) . 31 2/48 DS5877 Rev 13