STEVAL-ILL020V1 LCD panels backlight demonstration board based on the LED7706 Data brief Features Features boost section 4.5 V to 36 V input voltage range internal power MOSFET internal +5 V LDO for device supply up to 36 V output voltage constant frequency peak current-mode control 200 kHz to 1 MHz adjustable switching frequency external sync for multi-device application pulse-skip power saving mode at light load STEVAL-ILL020V1 programmable soft-start programmable OVP protection The generators can be externally programmed to single ceramic output capacitor sink up to 30 mA and can be dimmed via a PWM non-latched thermal shutdown signal (1% dimming duty cycle at 20 kHz can be Features backlight driver section managed). six rows with 30 mA maximum current The device allows to detect and manage the open capability (adjustable) and shorted LED faults and to let unused rows pp to 10 white LEDs per row floating. rows disable option Basic protections (output overvoltage, internal less than 500 ns minimum dimming time MOSFET overcurrent and thermal shutdown) are (1% minimum dimming duty-cycle at 20 provided. kHz dimming frequency) 2.0% current matching between rows LED failure (open and short circuit) detection RoHS compliant Description This demonstration board is based on the LED7706 and implements a high efficiency monolithic boost converter and six controlled current generators (rows) specifically designed to supply LEDs arrays used in the backlight of LCD panels. The device can manage an output voltage up to 36 V (i.e. ten white-LEDs per row). May 2009 Doc ID 15675 Rev 1 1/5 For further information contact your local STMicroelectronics sales office. www.st.com 5 Circuit schematic and PCB layout STEVAL-ILL020V1 1 Circuit schematic and PCB layout Figure 1. Schematic diagram 6 ) . , U 3 4 03 , - U 6 ) . 2 2 K K 3 9 . 6 6 * 3 , / 0 % 2 K U U . - 6 2 5 , % % . / 6 3 % , K P 2 . 8 ) , K N . 6 6 / / 3 4 9 2 % M 3 6 / 63% , 2 & 5 2 3 , / 0 % U . , / 0 . % . & 5 , 4 , % % . 2 / 7 2 / 7 ) - ) - 2 / 7 2 / 7 - / % 2 / 7 6 2 / 7 / - 0 / - 0 4 ( 0 * 3 3 ( % % 2 - ) - ) . 7 , 2 3 3 ) , 3 ) 3 7 3 7 & 2 3 K 2 K N % . 2 / 7 2 / 7 2 / 7 2 / 7 2 / 7 2 / 7 & 3 7 2 ) , ) - ) , ) - N . - N 3 7 2 2 2 K K K 6 ) . - V Figure 2. Top side component placement 2/5 Doc ID 15675 Rev 1 6 ,4