STEVAL-IPT004V1 24-pin smartcard interface demonstration board based on the ST8034HN Data brief Description The ST8034xx interface devices are placed between the smartcard and the microcontroller to provide all supply, protection, detection and control functions, with a minimum of external components. The STEVAL-IPT004V1 demonstration board allows designers to easily test all of these features, or it can be used as a functional block of a complete application as it is designed both for standalone operation or to be fully controlled by the microcontroller. The board is fully configurable to maintain flexibility for various use scenarios. It includes standard interfaces on both sides (smartcard connector, MCU interface connector) and labeled test points Features on all the signals to make them easily accessible. Connector for smartcard testing The STEVAL-IPT004V1 demonstration board Labeled test points for access to all signals addresses market segments such as POS, set- top box, pay TV, identification, banking and Board design allows standalone operation for tachograph. basic testing Interfacing to the MCU block and simple board configurability allows full function in (for example) a set-top box application On-board 10 MHz crystal clock oscillator can be used to provide card clock in standalone operation Card clock source selection switch allows selection between the on-board crystal oscillator as card clock source, or external clock source provided by the MCU block through the MCU interface together with the data signals Provides easy, flexible card supply voltage selection by on-board configuration switches, or remotely through the microcontroller RoHS compliant August 2013 DocID024484 Rev 1 1/4 For further information contact your local STMicroelectronics sales office. www.st.com 4 6 8 6 8 &/ 56 9& & & & & & & 8 8 7 / 8 ( 56 &/ &/ 9& 9& ( W 9 9 5 . ( Schematic diagram STEVAL-IPT004V1 1 Schematic diagram Figure 1. STEVAL-IPT004V1 circuit schematic & 7 & 6 2, *1 1* 6, / /&)) & 7 . 2, 6(5 * * * * Q X Q Q N N Q 7 . & 3 - 6 5 7 2)) *1 , 2 8 & 8 8 8& 8 , 2 8 8& 7 / 3 5( 6 7 / &/ . , 9 ,17) (/6 /(6 &9& 9 , &B 1,7 &B 0 . 3 6 N 7 Q N DO &ORFN VRX W UFH N 66 N 66 66 66 66 N * * * * 80 +0 6 * * * * S S N *1 * 1 9B && /6(B B9 /(6B&& 6666 6666 )71, 1 7), 8 9 8 9 9 1, 3 7) / 6(B & / (6B & & & 09 )) 2 , 28& B/ 6( / B(6 .9 , . , 9 7,1 && &8 8& - - - ( .5 1* 0/ : *1 * 1 1* 1* *1 2/4 DocID024484 Rev 1 *1 6 * 6 * 6 * 6 * *1 *1 & +1 *1 *1 9 32 9& 9 9 56 9& 9& *1 8 *1 & 56 &/ &/ *1 0& +1 6& 9& 5( &/ *1 1& *1 *1 1& 1& *1 3 3 3 *1 *1 *1 0& 6 6 * * 6 6 * * 6 6 * * 6 6 * * *1 *1 *1 *1 9& 9& 5 & & 5 5 5 5 5 5 5 560 5