STLUX285A STMicroelectronics

STLUX Digital controllers for lighting and power conversion applications with up to 6 programmable PWM generators, 96 MHz PLL, DALI Datasheet - production data Memories 2 Flash and E PROM with read while write (RWW) and error correction code (ECC) Program memory: 32 Kbytes Flash data retention 15 years at 85 C after 10 kcycles at 25 C 2 Data memory: 1 Kbyte true data E PROM Features data retention:15 years at 85 C after 100 kcycles at 85 C Up to 6 programmable PWM generators (SMEDs - State Machine Event Driven) RAM: 2 Kbytes 10 ns event detection and reaction Clock management Max.1.3 ns PWM resolution Internal 96 MHz PLL Single, coupled and two coupled Low power oscillator circuit for external operational modes crystal resonator or direct clock input Up to 3 internal/external events per SMED Internal, user-trimmable 16 MHz RC and low power 153.6 kHz RC oscillators DALI (digital addressable lighting interface) Clock security system with clock monitor Interrupt driven hardware encoder Bus frequency: 1.2, 2.4 or 4.8 kHz Basic peripherals IEC 60929 and IEC 62386 compliant plus System and auxiliary timers 24-bit frame extension IWDG/WWDG watchdog, AWU, ITC Configurable noise rejection filter I/O Reverse polarity on Tx/Rx lines GPIO with highly robust design, immune 4 analog comparators against current injection 4 internal 4-bit references Fast digital input DIGIN, with configurable pull-up 1 external reference Less than 50 ns propagation time Communication interfaces Continuous comparison cycle UART asynchronous with SW flow control and boot loader support ADCs (up to 8 channels) 2 I C master/slave fast-slow speed rate 10-bit precision, with operational amplifier to extend resolution to 12-bit equivalent Operating temperature: -40 C up to 105 C Sequencer functionality Table 1. Device summary Input impedance: 1 M Part number Package Configurable gain value: x1 and x4 Integrated microcontroller STLUX385A, STLUX383A TSSOP38 Advanced STM8 core with Harvard STLUX325A VFQFPN32 architecture and 3-stage pipeline STLUX285A TSSOP28 Max. f : 16 MHz CPU Multiple low power modes May 2015 DocID027870 Rev 1 1/126 This is information on a product in full production. www.st.comContents STLUX Contents 1 Description 10 2 STLUX family features list . 11 3 Introducing SMED 12 Documentation . 12 4 System architecture 13 Block diagram 14 5 Product overview 15 5.1 SMED (state machine event driven): configurable PWM generator . 15 5.1.1 SMED coupling schemes 15 5.1.2 Connection matrix . 16 Connection matrix interconnection . 18 5.2 Internal controller (CPU) 20 5.2.1 Architecture and registers . 20 5.2.2 Addressing . 20 5.2.3 Instruction set 20 5.2.4 Single wire interface module (SWIM) 20 5.2.5 Debug module 21 5.3 Basic peripherals . 21 5.3.1 Vectored interrupt controller 21 5.3.2 Timers 21 2 5.4 Flash program and data E PROM 22 5.4.1 Architecture 23 5.4.2 Write protection (WP) 23 5.4.3 Protection of user boot code (UBC) 23 5.4.4 Readout protection (ROP) . 24 5.5 Clock controller . 24 5.5.1 Internal 16 MHz RC oscillator (HSI) 24 5.5.2 Internal 153.6 kHz RC oscillator (LSI) 25 5.5.3 Internal 96 MHz PLL . 25 5.5.4 External clock input/crystal oscillator (HSE) . 25 2/126 DocID027870 Rev 1