STM32F100xC STM32F100xD STM32F100xE High-density value line, advanced Arm -based 32-bit MCU with 256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces Datasheet production data Features Core: Arm 32-bit Cortex -M3 CPU 24 MHz maximum frequency, 1.25 DMIPS /MHz (Dhrystone 2.1) performance LQFP144 LQFP100 LQFP64 20 20 mm Single-cycle multiplication and hardware 14 14 mm 10 10 mm division Up to 16 timers Memories Up to seven 16-bit timers, each with up to 4 256 to 512 Kbytes of Flash memory IC/OC/PWM or pulse counter 24 to 32 Kbytes of SRAM One 16-bit, 6-channel advanced-control Flexible static memory controller with 4 timer: up to 6 channels for PWM output, Chip Selects. Supports SRAM, PSRAM dead time generation and emergency stop and NOR memories One 16-bit timer, with 2 IC/OC, 1 LCD parallel interface, 8080/6800 modes OCN/PWM, dead-time generation and Clock, reset and supply management emergency stop 2.0 to 3.6 V application supply and I/Os Two 16-bit timers, each with POR, PDR and programmable voltage IC/OC/OCN/PWM, dead-time generation detector (PVD) and emergency stop 4-to-24 MHz crystal oscillator Two watchdog timers Internal 8 MHz factory-trimmed RC SysTick timer: 24-bit downcounter Internal 40 kHz RC Two 16-bit basic timers to drive the DAC PLL for CPU clock Up to 11 communications interfaces 2 32 kHz oscillator for RTC with calibration Up to two I C interfaces (SMBus/PMBus) Up to 3 USARTs (ISO 7816 interface, LIN, Low power IrDA capability, modem control) Sleep, Stop and Standby modes Up to 2 UARTs V supply for RTC and backup registers BAT Up to 3 SPIs (12 Mbit/s) Serial wire debug (SWD) and JTAG I/F Consumer electronics control (CEC) I/F DMA CRC calculation unit, 96-bit unique ID 12-channel DMA controller Peripherals supported: timers, ADC, SPIs, Table 1. Device summary 2 I Cs, USARTs and DACs Reference Part number 1 12-bit, 1.2 s A/D converter (up to 16 ch.) Conversion range: 0 to 3.6 V STM32F100RC, STM32F100VC, STM32F100xC Temperature sensor STM32F100ZC 2 12-bit D/A converters STM32F100RD, STM32F100VD, STM32F100xD STM32F100ZD Up to 112 fast I/O ports 51/80/112 I/Os, all mappable on 16 STM32F100RE, STM32F100VE, STM32F100xE external interrupt vectors and almost all STM32F100ZE 5 V-tolerant October 2018 DS5944 Rev 11 1/107 This is information on a product in full production. www.st.comContents STM32F100xC, STM32F100xD, STM32F100xE Contents 1 Introduction 9 2 Description 10 2.1 Device overview .11 2.2 Overview . 14 2.2.1 Arm Cortex-M3 core with embedded Flash and SRAM 14 2.2.2 Embedded Flash memory . 14 2.2.3 CRC (cyclic redundancy check) calculation unit 14 2.2.4 Embedded SRAM . 14 2.2.5 FSMC (flexible static memory controller) 14 2.2.6 LCD parallel interface 14 2.2.7 Nested vectored interrupt controller (NVIC) 15 2.2.8 External interrupt/event controller (EXTI) . 15 2.2.9 Clocks and startup . 15 2.2.10 Boot modes 15 2.2.11 Power supply schemes . 16 2.2.12 Power supply supervisor 16 2.2.13 Voltage regulator 16 2.2.14 Low-power modes . 16 2.2.15 DMA 17 2.2.16 RTC (real-time clock) and backup registers 17 2.2.17 Timers and watchdogs 17 2.2.18 I C bus 20 2.2.19 Universal synchronous/asynchronous receiver transmitter (USART) 20 2.2.20 Universal asynchronous receiver transmitter (UART) 20 2.2.21 Serial peripheral interface (SPI) . 20 2.2.22 HDMI (high-definition multimedia interface) consumer electronics control (CEC) 21 2.2.23 GPIOs (general-purpose inputs/outputs) 21 2.2.24 Remap capability 21 2.2.25 ADC (analog-to-digital converter) . 21 2.2.26 DAC (digital-to-analog converter) . 21 2.2.27 Temperature sensor 22 2.2.28 Serial wire JTAG debug port (SWJ-DP) . 22 2/107 DS5944 Rev 11