STM32F101x4 STM32F101x6 Low-density access line, ARM -based 32 bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces Datasheet - production data Features Core: ARM 32-bit Cortex -M3 CPU 36 MHz maximum frequency, LQFP48 1.25 DMIPS/MHz (Dhrystone 2.1) LQFP64 VFQFPN36 7 x 7 mm 10 x 10 mm 6 6 mm performance at 0 wait state memory access Single-cycle multiplication and hardware Up to 5 timers division Up to two16-bit timers, each with up to 4 IC/OC/PWM or pulse counter Memories 2 watchdog timers (Independent and 16 to 32 Kbytes of Flash memory Window) 4 to 6 Kbytes of SRAM SysTick timer: 24-bit downcounter Clock, reset and supply management Up to 4 communication interfaces 2.0 to 3.6 V application supply and I/Os 2 1 x I C interface (SMBus/PMBus) POR, PDR and programmable voltage Up to 2 USARTs (ISO 7816 interface, LIN, detector (PVD) IrDA capability, modem control) 4-to-16 MHz crystal oscillator 1 SPI (18 Mbit/s) Internal 8 MHz factory-trimmed RC CRC calculation unit, 96-bit unique ID Internal 40 kHz RC PLL for CPU clock ECOPACK packages 32 kHz oscillator for RTC with calibration Table 1. Device summary Low power Reference Part number Sleep, Stop and Standby modes V supply for RTC and backup registers BAT STM32F101C4, STM32F101x4 STM32F101R4, Debug mode STM32F101T4 Serial wire debug (SWD) and JTAG interfaces STM32F101C6, STM32F101x6 STM32F101R6, DMA STM32F101T6 7-channel DMA controller Peripherals supported: timers, ADC, SPIs, 2 I Cs and USARTs 1 12-bit, 1 s A/D converter (up to 16 channels) Conversion range: 0 to 3.6 V Temperature sensor Up to 51 fast I/O ports 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant September 2015 DocID15058 Rev 6 1/87 This is information on a product in full production. www.st.comContents STM32F101x4, STM32F101x6 Contents 1 Introduction 9 2 Description 10 2.1 Device overview .11 2.2 Full compatibility throughout the family 14 2.3 Overview . 15 2.3.1 ARM Cortex -M3 core with embedded Flash and SRAM . 15 2.3.2 Embedded Flash memory . 15 2.3.3 CRC (cyclic redundancy check) calculation unit 15 2.3.4 Embedded SRAM . 15 2.3.5 Nested vectored interrupt controller (NVIC) 15 2.3.6 External interrupt/event controller (EXTI) . 16 2.3.7 Clocks and startup . 16 2.3.8 Boot modes 16 2.3.9 Power supply schemes . 16 2.3.10 Power supply supervisor 16 2.3.11 Voltage regulator 17 2.3.12 Low-power modes . 17 2.3.13 DMA 17 2.3.14 RTC (real-time clock) and backup registers 18 2.3.15 Independent watchdog . 18 2.3.16 Window watchdog . 18 2.3.17 SysTick timer . 18 2.3.18 General-purpose timers (TIMx) . 18 2.3.19 I C bus 19 2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) 19 2.3.21 Serial peripheral interface (SPI) . 19 2.3.22 GPIOs (general-purpose inputs/outputs) 19 2.3.23 ADC (analog to digital converter) 19 2.3.24 Temperature sensor 20 2.3.25 Serial wire JTAG debug port (SWJ-DP) . 20 3 Pinouts and pin description 21 2/87 DocID15058 Rev 6