STM32F101x8 STM32F101xB Medium-density access line, ARM -based 32-bit MCU with 64 or 128 KB Flash, 6 timers, ADC and 7 communication interfaces Datasheet - production data Features Core: ARM 32-bit Cortex -M3 CPU 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) LQFP100 LQFP64 performance at 0 wait state memory 14 x 14 mm 10 x 10 mm access Single-cycle multiplication and hardware division Memories LQFP48 UFQFPN48 VFQFPN36 7 x 7 mm 7 7 mm 6 6 mm 64 to 128 Kbytes of Flash memory 10 to 16 Kbytes of SRAM 26/37/51/80 I/Os, all mappable on 16 Clock, reset and supply management external interrupt vectors and almost all 2.0 to 3.6 V application supply and I/Os 5 V-tolerant POR, PDR and programmable voltage Six timers detector (PVD) Three 16-bit timers, each with up to 4 4-to-16 MHz crystal oscillator IC/OC/PWM or pulse counter Internal 8 MHz factory-trimmed RC 2 watchdog timers (Independent and Internal 40 kHz RC Window) PLL for CPU clock SysTick timer: 24-bit downcounter 32 kHz oscillator for RTC with calibration Up to 7 communication interfaces 2 Low power Up to 2 x I C interfaces (SMBus/PMBus) Sleep, Stop and Standby modes Up to 3 USARTs (ISO 7816 interface, LIN, V supply for RTC and backup registers IrDA capability, modem control) BAT Up to 2 SPIs (18 Mbit/s) Debug mode Serial wire debug (SWD) and JTAG CRC calculation unit, 96-bit unique ID interfaces ECOPACK packages DMA Table 1. Device summary 7-channel DMA controller Peripherals supported: timers, ADC, SPIs, Reference Part number 2 I Cs and USARTs STM32F101C8, 1 12-bit, 1 s A/D converter (up to 16 STM32F101R8 STM32F101x8 channels) STM32F101V8, Conversion range: 0 to 3.6 V STM32F101T8 Temperature sensor STM32F101RB, STM32F101VB, Up to 80 fast I/O ports STM32F101xB STM32F101CB STM32F101TB June 2015 DocID13586 Rev 17 1/101 This is information on a product in full production. www.st.comContents STM32F101x8, STM32F101xB Contents 1 Introduction 9 2 Description 10 2.1 Device overview .11 2.2 Full compatibility throughout the family 14 2.3 Overview . 15 2.3.1 ARM Cortex -M3 core with embedded Flash and SRAM . 15 2.3.2 Embedded Flash memory . 15 2.3.3 CRC (cyclic redundancy check) calculation unit 15 2.3.4 Embedded SRAM . 15 2.3.5 Nested vectored interrupt controller (NVIC) 15 2.3.6 External interrupt/event controller (EXTI) . 16 2.3.7 Clocks and startup . 16 2.3.8 Boot modes 16 2.3.9 Power supply schemes . 16 2.3.10 Power supply supervisor 16 2.3.11 Voltage regulator 17 2.3.12 Low-power modes . 17 2.3.13 DMA 18 2.3.14 RTC (real-time clock) and backup registers 18 2.3.15 Independent watchdog . 18 2.3.16 Window watchdog . 18 2.3.17 SysTick timer . 19 2.3.18 General-purpose timers (TIMx) . 19 2.3.19 I C bus 19 2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) 19 2.3.21 Serial peripheral interface (SPI) . 19 2.3.22 GPIOs (general-purpose inputs/outputs) 19 2.3.23 ADC (analog to digital converter) 20 2.3.24 Temperature sensor 20 2.3.25 Serial wire JTAG debug port (SWJ-DP) . 20 3 Pinouts and pin description 21 2/101 DocID13586 Rev 17