STM32F215xx STM32F217xx ARM -based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features . Core: ARM 32-bit Cortex -M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution performance from Flash memory, MPU, LQFP64 (10 10 mm) 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1) LQFP100 (14 14 mm) UFBGA176 (10 10 mm) Memories LQFP144 (20 20 mm) Up to 1 Mbyte of Flash memory LQFP176 (24 24 mm) 512 bytes of OTP memory Up to 128 + 4 Kbytes of SRAM Up to 140 I/O ports with interrupt capability: Flexible static memory controller that Up to 136 fast I/Os up to 60 MHz supports Compact Flash, SRAM, PSRAM, Up to 138 5 V-tolerant I/Os NOR and NAND memories Up to 15 communication interfaces LCD parallel interface, 8080/6800 modes 2 Up to three I C interfaces (SMBus/PMBus) Clock, reset and supply management Up to four USARTs and two UARTs From 1.8 to 3.6 V application supply + I/Os (7.5 Mbit/s, ISO 7816 interface, LIN, IrDA, POR, PDR, PVD and BOR modem control) 4 to 26 MHz crystal oscillator Up to three SPIs (30 Mbit/s), two with 2 Internal 16 MHz factory-trimmed RC muxed I S to achieve audio class accuracy 32 kHz oscillator for RTC with calibration via audio PLL or external PLL Internal 32 kHz RC with calibration 2 CAN interfaces (2.0B Active) SDIO interface Low-power modes Sleep, Stop and Standby modes Advanced connectivity V supply for RTC, 20 32 bit backup USB 2.0 full-speed device/host/OTG BAT registers, and optional 4 Kbytes backup controller with on-chip PHY SRAM USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated 3 12-bit, 0.5 s ADCs with up to 24 channels DMA, on-chip full-speed PHY and ULPI and up to 6 MSPS in triple interleaved mode 10/100 Ethernet MAC with dedicated DMA: 2 12-bit D/A converters supports IEEE 1588v2 hardware, MII/RMII General-purpose DMA: 16-stream controller 8- to 14-bit parallel camera interface with centralized FIFOs and burst support (48 Mbyte/s max.) Up to 17 timers Cryptographic acceleration Up to twelve 16-bit and two 32-bit timers, Hardware acceleration for AES 128, 192, up to 120 MHz, each with up to four 256, Triple DES, HASH (MD5, SHA-1) IC/OC/PWM or pulse counter and Analog true random number generator quadrature (incremental) encoder input CRC calculation unit Debug mode: Serial wire debug (SWD), JTAG, and Cortex -M3 Embedded Trace Macrocell 96-bit unique ID August 2016 DocID17050 Rev 13 1/180 This is information on a product in full production. www.st.comSTM32F21xxx Table 1. Device summary Reference Part numbers STM32F215RG, STM32F215VG, STM32F215ZG STM32F215xx STM32F215RE, STM32F215VE, STM32F215ZE STM32F217VG, STM32F217IG, STM32F217ZG STM32F217xx STM32F217VE, STM32F217IE, STM32F217ZE 2/180 DocID17050 Rev 13