STM32F413xG STM32F413xH Arm -Cortex -M4 32b MCU+FPU, 125 DMIPS, up to 1.5MB Flash, 320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs Datasheet - production data Features )%* Dynamic Efficiency Line with eBAM (enhanced Batch Acquisition Mode) UFBGA100 LQFP64 (10x10mm) 1.7 V to 3.6 V power supply WLCSP81 UFQFPN48 (7x7mm) LQFP100 (14x14mm) (4.039x3.951 mm) (7x7 mm) UFBGA144 -40 C to 85/105/125 C temperature range LQFP144 (20x20mm) (10x10mm) Core: Arm 32-bit Cortex -M4 CPU with FPU, Up to 18 timers: up to twelve 16-bit timers, two Adaptive real-time accelerator (ART 32-bit timers up to 100 MHz each with up to Accelerator) allowing 0-wait state execution four IC/OC/PWM or pulse counter and from Flash memory, frequency up to 100 MHz, quadrature (incremental) encoder input, two memory protection unit, 125 DMIPS/ watchdog timers (independent and window), 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP one SysTick timer, and a low-power timer instructions Debug mode Memories Serial wire debug (SWD) & JTAG Up to 1.5 Mbytes of Flash memory Cortex -M4 Embedded Trace Macrocell 320 Kbytes of SRAM Up to 114 I/O ports with interrupt capability Flexible external static memory controller with up to 16-bit data bus: SRAM, PSRAM, Up to 109 fast I/Os up to 100 MHz NOR Flash memory Up to 114 five V-tolerant I/Os Dual mode Quad-SPI interface Up to 24 communication interfaces 2 LCD parallel interface, 8080/6800 modes Up to 4x I C interfaces (SMBus/PMBus) Clock, reset and supply management Up to 10 UARTS: 4 USARTs / 6 UARTs (2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816 1.7 to 3.6 V application supply and I/Os interface, LIN, IrDA, modem control) POR, PDR, PVD and BOR Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or 4-to-26 MHz crystal oscillator I2S audio protocol), out of which 2 muxed Internal 16 MHz factory-trimmed RC full-duplex I2S interfaces 32 kHz oscillator for RTC with calibration SDIO interface (SD/MMC/eMMC) Internal 32 kHz RC with calibration Advanced connectivity: USB 2.0 full-speed Power consumption device/host/OTG controller with PHY Run: 112 A/MHz (peripheral off) 3x CAN (2.0B Active) Stop (Flash in Stop mode, fast wakeup 1xSAI time): 42 A Typ. 80 A max 25 C True random number generator Stop (Flash in Deep power down mode, CRC calculation unit slow wakeup time): 15 A Typ. 96-bit unique ID 46 A max 25 C RTC: subsecond accuracy, hardware calendar Standby without RTC: 1.1 A Typ. 14.7 A max at 85 C All packages are ECOPACK 2 V supply for RTC: 1 A 25 C BAT Table 1. Device summary 2x12-bit D/A converters Reference Part number 112-bit, 2.4 MSPS ADC: up to 16 channels 6x digital filters for sigma delta modulator, STM32F413CH STM32F413MH STM32F413RH STM32F413xH 12x PDM interfaces, with stereo microphone STM32F413VH STM32F413ZH and sound source localization support STM32F413CG STM32F413MG STM32F413RG STM32F413xG STM32F413VG STM32F413ZG General-purpose DMA: 16-stream DMA September 2017 DocID029162 Rev 6 1/208 This is information on a product in full production. www.st.comContents STM32F413xG/H Contents 1 Introduction . 12 2 Description 13 2.1 Compatibility with STM32F4 series . 16 3 Functional overview 19 3.1 Arm Cortex -M4 with FPU core with embedded Flash and SRAM 19 3.2 Adaptive real-time memory accelerator (ART Accelerator) . 19 3.3 Enhanced Batch Acquisition mode (eBAM) . 19 3.4 Memory protection unit . 20 3.5 Embedded Flash memory 20 3.6 CRC (cyclic redundancy check) calculation unit . 20 3.7 Embedded SRAM . 21 3.8 Multi-AHB bus matrix 21 3.9 DMA controller (DMA) . 22 3.10 Flexible static memory controller (FSMC) 22 3.11 Quad-SPI memory interface (QUAD-SPI) 23 3.12 Nested vectored interrupt controller (NVIC) . 23 3.13 External interrupt/event controller (EXTI) . 23 3.14 Clocks and startup 23 3.15 Boot modes . 24 3.16 Power supply schemes 25 3.17 Power supply supervisor . 26 3.17.1 Internal reset ON 26 3.17.2 Internal reset OFF . 27 3.18 Voltage regulator . 27 3.18.1 Regulator ON . 28 3.18.2 Regulator OFF 28 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability 31 3.19 Real-time clock (RTC) and backup registers 31 3.20 Low-power modes 32 3.21 VBAT operation 32 2/208 DocID029162 Rev 6