STM32G0B0KE/CE/RE/VE Arm Cortex -M0+ 32-bit MCU, 512KB Flash, 144KB RAM, 6x USART, timers, ADC, comm. I/Fs, 2.0-3.6V Datasheet - production data Features LQFP32 7 7mm LQFP48 7 7mm Core: Arm 32-bit Cortex -M0+ CPU, frequency up to 64 MHz LQFP64 10 10 mm LQFP100 14 14 mm -40C to 85C operating temperature Memories Communication interfaces 512 Kbytes of Flash memory with 2 Three I C-bus interfaces supporting Fast- protection, two banks, read-while-write mode Plus (1 Mbit/s) with extra current support sink, two supporting SMBus/PMBus and 144 Kbytes of SRAM (128 Kbytes with HW wakeup from Stop mode parity check) Six USARTs with master/slave CRC calculation unit synchronous SPI three supporting ISO7816 interface, LIN, IrDA capability, Reset and power management auto baud rate detection and wakeup Voltage range: 2.0 V to 3.6 V feature Power-on/Power-down reset (POR/PDR) Three SPIs (32 Mbit/s) with 4- to 16-bit Low-power modes: programmable bitframe, two multiplexed Sleep, Stop, Standby 2 with I S interface V supply for RTC and backup registers BAT USB 2.0 FS device and host controller Clock management Development support: serial wire debug (SWD) 4 to 48 MHz crystal oscillator 32 kHz crystal oscillator with calibration All packages ECOPACK 2 compliant Internal 16 MHz RC with PLL option (5 %) Internal 32 kHz RC oscillator (5 %) Up to 93 fast I/Os All mappable on external interrupt vectors Multiple 5 V-tolerant I/Os 12-channel DMA controller with flexible mapping 12-bit, 0.4 s ADC (up to 16 ext. channels) Up to 16-bit with hardware oversampling Conversion range: 0 to 3.6V 12 timers: 16-bit for advanced motor control, six 16-bit general-purpose, two basic 16-bit, two watchdogs, SysTick timer Calendar RTC with alarm and periodic wakeup from Stop/Standby February 2021 DS13565 Rev 2 1/105 This is information on a product in full production. www.st.comContents STM32G0B0KE/CE/RE/VE Contents 1 Introduction 8 2 Description . 9 3 Functional overview 12 3.1 Arm Cortex -M0+ core with MPU . 12 3.2 Memory protection unit . 12 3.3 Embedded Flash memory 12 3.4 Embedded SRAM . 13 3.5 Boot modes . 14 3.6 Cyclic redundancy check calculation unit (CRC) . 14 3.7 Power supply management . 14 3.7.1 Power supply schemes . 14 3.7.2 Power supply supervisor 15 3.7.3 Voltage regulator 15 3.7.4 Low-power modes . 16 3.7.5 Reset mode 17 3.7.6 VBAT operation . 17 3.8 Interconnect of peripherals 17 3.9 Clocks and startup 18 3.10 General-purpose inputs/outputs (GPIOs) . 19 3.11 Direct memory access controller (DMA) 19 3.12 DMA request multiplexer (DMAMUX) 20 3.13 Interrupts and events 20 3.13.1 Nested vectored interrupt controller (NVIC) 20 3.13.2 Extended interrupt/event controller (EXTI) 21 3.14 Analog-to-digital converter (ADC) 21 3.14.1 Temperature sensor 22 3.14.2 Internal voltage reference (V ) . 22 REFINT 3.14.3 V battery voltage monitoring . 22 BAT 3.15 Timers and watchdogs . 22 3.15.1 Advanced-control timer (TIM1) . 23 3.15.2 General-purpose timers (TIM3, 4, 14, 15, 16, 17) . 23 2/105 DS13565 Rev 2