STM32G4A1xE Arm Cortex -M4 32-bit MCU+FPU, 170 MHz / 213 DMIPS, up to 512 KB Flash, 112 KB SRAM, rich analog, math accelerator, AES Datasheet - production data Features FBGA Includes ST state-of-the-art patented technology LQFP48 (7 x 7 mm) UFBGA64 UFQFPN32 (5 x 5 mm) WLCSP64 Core: Arm 32-bit Cortex -M4 CPU with FPU, (Pitch 0.4) LQFP64 (10 x 10 mm) UFQFPN48 (7 x 7 mm) (5 x 5 mm) LQFP80 (12 x 12 mm) Adaptive real-time accelerator (ART LQFP80 (14 x 14 mm) Accelerator) allowing 0-wait-state execution LQFP100 (14 x 14 mm) from Flash memory, frequency up to 170 MHz with 213 DMIPS, MPU, DSP instructions Up to 86 fast I/Os All mappable on external interrupt vectors Operating conditions: Several I/Os with 5 V tolerant capability V , V voltage range: DD DDA 1.71 V to 3.6 V Interconnect matrix Mathematical hardware accelerators 16-channel DMA controller CORDIC for trigonometric functions 3 x ADCs 0.25 s (up to 36 channels). acceleration Resolution up to 16-bit with hardware FMAC: filter mathematical accelerator oversampling, 0 to 3.6 V conversion range Memories 4 x 12-bit DAC channels 512 Kbytes of Flash memory with ECC 2 x buffered external channels 1 MSPS support, proprietary code readout 2 x unbuffered internal channels 15 MSPS protection (PCROP), securable memory 4 x ultra-fast rail-to-rail analog comparators area, 1 Kbyte OTP 4 x operational amplifiers that can be used in 96 Kbytes of SRAM, with hardware parity PGA mode, all terminals accessible check implemented on the first 32 Kbytes Routine booster: 16 Kbytes of SRAM on Internal voltage reference buffer (VREFBUF) instruction and data bus, with hardware supporting three output voltages (2.048 V, parity check (CCM SRAM) 2.5 V, 2.9 V) Quad-SPI memory interface 15 timers: Reset and supply management 1 x 32-bit timer and 2 x 16-bit timers with up Power-on/power-down reset to four IC/OC/PWM or pulse counter and (POR/PDR/BOR) quadrature (incremental) encoder input 3 x 16-bit 8-channel advanced motor Programmable voltage detector (PVD) control timers, with up to 8 x PWM Low-power modes: sleep, stop, standby channels, dead time generation and and shutdown emergency stop V supply for RTC and backup registers BAT 1 x 16-bit timer with 2 x IC/OCs, one Clock management OCN/PWM, dead time generation and 4 to 48 MHz crystal oscillator emergency stop 32 kHz oscillator with calibration 2 x 16-bit timers with IC/OC/OCN/PWM, Internal 16 MHz RC with PLL option ( 1%) dead time generation and emergency stop Internal 32 kHz RC oscillator ( 5%) 2 x watchdog timers (independent, window) September 2021 DS13268 Rev 3 1/200 This is information on a product in full production. www.st.comSTM32G4A1xE 1 x SysTick timer: 24-bit downcounter 3 x SPIs, 4 to 16 programmable bit frames, 2 2 x with multiplexed half duplex I S 2 x 16-bit basic timers interface 1 x low-power timer 1 x SAI (serial audio interface) Calendar RTC with alarm, periodic wakeup USB 2.0 full-speed interface with LPM and from stop/standby BCD support Communication interfaces IRTIM (infrared interface) 2 x FDCAN controller supporting flexible USB Type-C /USB power delivery data rate controller (UCPD) 2 3 x I C Fast mode plus (1 Mbit/s) with True random number generator (RNG) 20 mA current sink, SMBus/PMBus, wakeup from stop CRC calculation unit, 96-bit unique ID 5 x USART/UARTs (ISO 7816 interface, AES: 128/256-bit key encryption hardware LIN, IrDA, modem control) accelerator 1 x LPUART Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell Table 1. Device summary Reference Part number STM32G4A1xE STM32G4A1CE, STM32G4A1KE, STM32G4A1ME, STM32G4A1RE, STM32G4A1VE 2/200 DS13268 Rev 3