STM32H730AB STM32H730IB STM32H730VB STM32H730ZB Arm Cortex -M7 32b 550 MHz MCU, 128 KB Flash, 564 KB RAM, Ethernet, USB, 3xFD-CAN, Graphics, 2x16b ADCs, crypto/hash Datasheet - production data Features FBGA Includes ST state-of-the-art patented technology LQFP100 (14 x 14 mm) TFBGA100 (8 x 8 mm) Core LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) 32-bit Arm Cortex -M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte FBGA instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, UFBGA144 (7 x 7 mm) MPU, 1177 DMIPS/2.14 DMIPS/MHz UFBGA 169 (7 x 7 mm) UFBGA 176+25 (10 x 10 mm) (Dhrystone 2.1), and DSP instructions Memories 128 Kbytes of embedded Flash memory with Clock, reset and supply management ECC 1.62 V to 3.6 V application supply and I/O SRAM: total 564 Kbytes all with ECC, including POR, PDR, PVD and BOR 128 Kbytes of data TCM RAM for critical real- time data + 432 Kbytes of system RAM (up to Dedicated USB power 256 Kbytes can remap on instruction TCM Embedded DCDC and LDO regulator RAM for critical real time instructions) + Internal oscillators: 64 MHz HSI, 48 MHz 4 Kbytes of backup SRAM (available in the HSI48, 4 MHz CSI, 32 kHz LSI lowest-power modes) External oscillators: 4-50 MHz HSE, Flexible external memory controller with up to 32.768 kHz LSE 24-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Low power memories Sleep, Stop and Standby modes 2 x Octo-SPI interface with XiP and on-the-fly decryption support V supply for RTC, 3232-bit backup BAT registers 2 x SD/SDIO/MMC interface Bootloader with security services support (SFI Analog and SB-SFU) 216-bit ADC, up to 3.6 MSPS in 16-bit: up to 22 channels and 7.2 MSPS in double- Graphics interleaved mode Chrom-ART Accelerator graphical hardware 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 accelerator enabling enhanced graphical user channels interface to reduce CPU load 2 x comparators LCD-TFT controller supporting up to XGA resolution 2 x operational amplifier GBW = 8 MHz December 2021 DS13315 Rev 3 1/270 www.st.comSTM32H730xB 2 12-bit D/A converters DMA, on-chip FS PHY and ULPI for external HS PHY Digital filters for sigma delta modulator SWPMI single-wire protocol master I/F (DFSDM) MDIO slave interface 8 channels/4 filters Mathematical acceleration 4 DMA controllers to offload the CPU CORDIC for trigonometric functions 1 MDMA with linked list support acceleration 2 dual-port DMAs with FIFO FMAC: Filter mathematical accelerator 1 basic DMA with request router capabilities Digital temperature sensor 24 timers Cryptographic/HASH acceleration Seventeen 16-bit (including 5 x low power AES 128, 192, 256, TDES, HASH (MD5, SHA- 16-bit timer available in stop mode) and four 1, SHA-2), HMAC 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) 2x OTFDEC AES-128 in CTR mode for Octo- encoder input SPI memory encryption/decryption 2x watchdogs, 1x SysTick timer True random number generator Debug mode CRC calculation unit SWD and JTAG interfaces 2-Kbyte embedded trace buffer RTC with sub-second accuracy and hardware calendar Up to 128 I/O ports with interrupt capability ROP, PC-ROP, tamper detection, secure firmware upgrade support Up to 35 communication interfaces 96-bit unique ID Up to 5 I2C FM+ interfaces (SMBus/PMBus) All packages are ECOPACK2 compliant Up to 5 USARTs/5 UARTs (ISO7816 interface, LIN, IrDA, modem control) and 1 x LPUART Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or external clock and up to 5 x SPI (from 5 x USART when configured in synchronous mode) 2x SAI (serial audio interface) 1 FD/TT-CAN and 2x FD-CAN 8- to 14-bit camera interface 16-bit parallel slave synchronous interface SPDIF-IN interface HDMI-CEC Ethernet MAC interface with DMA controller USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated 2/270 DS13315 Rev 3