STM32H735xG Arm Cortex -M7 32-bit 550 MHz MCU, 1 MB Flash, 564 KB RAM, Ethernet, USB, 3x FD-CAN, Graphics, 2x1 6-bit ADCs, crypto/hash Datasheet - production data Features Includes ST state-of-the-art patented technology LQFP100 (14 x 14 mm) VFQFPN 68 LQFP144 (20 x 20 mm) Core (8x8 mm) LQFP176 (24 x 24 mm) 32-bit Arm Cortex -M7 CPU with DP-FPU, L1 FBGA FBGA cache: 32-Kbyte data cache and 32-Kbyte instruction cache allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 550 MHz, UFBGA 169 (7 x 7 mm) TFBGA100 UFBGA 176+25 (10 x 10 mm) MPU, 1177 DMIPS/2.14 DMIPS/MHz (8x8 mm) (Dhrystone 2.1), and DSP instructions Memories 1 Mbyte of embedded Flash memory with ECC SRAM: total 564 Kbytes all with ECC, including 128 Kbytes of data TCM RAM for critical real- time data + 432 Kbytes of system RAM (up to Clock, reset and supply management 256 Kbytes can remap on instruction TCM RAM for critical real time instructions) + 1.62 V to 3.6 V application supply and I/O 4 Kbytes of backup SRAM (available in the POR, PDR, PVD and BOR lowest-power modes) Dedicated USB power Flexible external memory controller with up to 24-bit data bus: SRAM, PSRAM, Embedded DCDC and LDO regulator SDRAM/LPSDR SDRAM, NOR/NAND (*)VFQFPN68 variant is DCDC only memories Internal oscillators: 64 MHz HSI, 48 MHz 2 x Octo-SPI interface with XiP and on-the-fly HSI48, 4 MHz CSI, 32 kHz LSI decryption support External oscillators: 4-50 MHz HSE, 2 x SD/SDIO/MMC interface 32.768 kHz LSE Bootloader with security services support (SFI Low power and SB-SFU) Sleep, Stop and Standby modes Graphics V supply for RTC, 3232-bit backup BAT Chrom-ART Accelerator graphical hardware registers accelerator enabling enhanced graphical user interface to reduce CPU load Analog LCD-TFT controller supporting up to XGA 216-bit ADC, up to 3.6 MSPS in 16-bit: up to resolution 22 channels and 7.2 MSPS in double- interleaved mode December 2021 DS13312 Rev 3 1/284 www.st.com WLCSP 115 0.35 mm pitchSTM32H735xG 1 x 12-bit ADC, up to 5 MSPS in 12-bit, up to 12 2x SAI (serial audio interface) channels 1 FD/TT-CAN and 2x FD-CAN 2 x comparators 8- to 14-bit camera interface 2 x operational amplifier GBW = 8 MHz 16-bit parallel slave synchronous interface 2 12-bit D/A converters SPDIF-IN interface HDMI-CEC Digital filters for sigma delta modulator (DFSDM) Ethernet MAC interface with DMA controller USB 2.0 high-speed/full-speed 8 channels/4 filters device/host/OTG controller with dedicated DMA, on-chip FS PHY and ULPI for external 4 DMA controllers to offload the CPU HS PHY 1 MDMA with linked list support SWPMI single-wire protocol master I/F 2 dual-port DMAs with FIFO MDIO slave interface 1 basic DMA with request router capabilities Mathematical acceleration 24 timers CORDIC for trigonometric functions Seventeen 16-bit (including 5 x low power acceleration 16-bit timer available in stop mode) and four FMAC: Filter mathematical accelerator 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) Digital temperature sensor encoder input 2x watchdogs, 1x SysTick timer Cryptographic/HASH acceleration AES 128, 192, 256, TDES, HASH (MD5, SHA- Debug mode 1, SHA-2), HMAC SWD and JTAG interfaces 2x OTFDEC AES-128 in CTR mode for Octo- 2-Kbyte embedded trace buffer SPI memory encryption/decryption Up to 128 I/O ports with interrupt True random number generator capability CRC calculation unit Up to 35 communication interfaces RTC with sub-second accuracy and Up to 5 I2C FM+ interfaces hardware calendar (SMBus/PMBus) Up to 5 USARTs/5 UARTs (ISO7816 interface, ROP, PC-ROP, tamper detection, secure LIN, IrDA, modem control) and 1 x LPUART firmware upgrade support Up to 6 SPIs with 4 with muxed duplex I2S for audio class accuracy via internal audio PLL or 96-bit unique ID external clock and up to 5 x SPI (from 5 x USART when configured in synchronous All packages are ECOPACK2 compliant mode) Table 1. Device summary Reference Part number STM32H735AG, STM32H735IG, STM32H735RG, STM32H735xG STM32H735VG, STM32H735ZG 2/284 DS13312 Rev 3