STM32H745xI/G Dual 32-bit Arm Cortex -M7 up to 480MHz and -M4 MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces, SMPS Datasheet - production data Features FBGA FBGA Dual core UFBGA176+25 LQFP144 TFBGA240+25 (10x10 mm) 32-bit Arm Cortex -M7 core with double- (20x20 mm) (14x14 mm) LQFP176 precision FPU and L1 cache: 16 Kbytes of data (24x24 mm) and 16 Kbytes of instruction cache frequency LQFP208 (28x28 mm) up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions Reset and power management 32-bit Arm 32-bit Cortex -M4 core with FPU, 3 separate power domains which can be Adaptive real-time accelerator (ART independently clock-gated or switched off: Accelerator) for internal Flash memory and D1: high-performance capabilities external memories, frequency up to 240 MHz, D2: communication peripherals and timers MPU, 300 DMIPS/1.25 DMIPS /MHz D3: reset/clock control/power management (Dhrystone 2.1), and DSP instructions 1.62 to 3.6 V application supply and I/Os Memories POR, PDR, PVD and BOR Up to 2 Mbytes of Flash memory with read- Dedicated USB power embedding a 3.3 V while-write support internal regulator to supply the internal PHYs 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. Embedded regulator (LDO) to supply the digital 64 Kbytes of ITCM RAM + 128 Kbytes of circuitry DTCM RAM for time critical routines), High power-efficiency SMPS step-down 864 Kbytes of user SRAM, and 4 Kbytes of converter regulator to directly supply V CORE SRAM in Backup domain and/or external circuitry Dual mode Quad-SPI memory interface Voltage scaling in Run and Stop mode (6 running up to 133 MHz configurable ranges) Flexible external memory controller with up to Backup regulator (~0.9 V) 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash Voltage reference for analog peripheral/V REF+ memory clocked up to 125 MHz in 1.2 to 3.6 V V supply BAT Synchronous mode Low-power modes: Sleep, Stop, Standby and CRC calculation unit V supporting battery charging BAT Security Low-power consumption ROP, PC-ROP, active tamper V battery operating mode with charging BAT capability General-purpose input/outputs CPU and domain power state monitoring pins Up to 168 I/O ports with interrupt capability 2.95 A in Standby mode (Backup SRAM OFF, RTC/LSE ON) May 2019 DS12923 Rev 1 1/252 This is information on a product in full production. www.st.comSTM32H745xI/G Clock management 2 operational amplifiers (7.3 MHz bandwidth) 1 digital filters for sigma delta modulator Internal oscillators: 64 MHz HSI, 48 MHz (DFSDM) with 8 channels/4 filters HSI48, 4 MHz CSI, 32 kHz LSI External oscillators: 4-48 MHz HSE, Graphics 32.768 kHz LSE LCD-TFT controller up to XGA resolution 3 PLLs (1 for the system clock, 2 for kernel Chrom-ART graphical hardware Accelerator clocks) with Fractional mode (DMA2D) to reduce CPU load Interconnect matrix Hardware JPEG Codec 3 bus matrices (1 AXI and 2 AHB) Up to 22 timers and watchdogs Bridges (5 AHB2-APB, 2 AXI2-AHB) 1 high-resolution timer (2.1 ns max 4 DMA controllers to unload the CPU resolution) 1 high-speed master direct memory access 2 32-bit timers with up to 4 IC/OC/PWM or controller (MDMA) with linked list support pulse counter and quadrature (incremental) encoder input (up to 240 MHz) 2 dual-port DMAs with FIFO 2 16-bit advanced motor control timers (up to 1 basic DMA with request router capabilities 240 MHz) Up to 35 communication peripherals 10 16-bit general-purpose timers (up to 240 MHz) 4 I2Cs FM+ interfaces (SMBus/PMBus) 5 16-bit low-power timers (up to 240 MHz) 4 USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART 4 watchdogs (independent and window) 6 SPIs, 3 with muxed duplex I2S audio class 2 SysTick timers accuracy via internal audio PLL or external RTC with sub-second accuracy and hardware clock, 1x I2S in LP domain (up to 150 MHz) calendar 4x SAIs (serial audio interface) Debug mode SPDIFRX interface SWD & JTAG interfaces SWPMI single-wire protocol master I/F 4-Kbyte Embedded Trace Buffer MDIO Slave interface 2 SD/SDIO/MMC interfaces (up to 125 MHz) True random number generators (3 2 CAN controllers: 2 with CAN FD, 1 with oscillators each) time-triggered CAN (TT-CAN) 96-bit unique ID 2 USB OTG interfaces (1FS, 1HS/FS) crystal- less solution with LPM and BCD Optional support of extended temperature Ethernet MAC interface with DMA controller range up to 125 C (specific part numbers) HDMI-CEC All packages are ECOPACK 2 compliant 8- to 14-bit camera interface (up to 80 MHz) Table 1. Device summary 11 analog peripherals Reference Part number 3 ADCs with 16-bit max. resolution (up to 36 STM32H745ZI, STM32H745II, channels, up to 3.6 MSPS) STM32H745xI STM32H745BI, STM32H745XI 1 temperature sensor STM32H745ZG, STM32H745IG, 2 12-bit D/A converters (1 MHz) STM32H745xG STM32H745BG, STM32H745XG 2 ultra-low-power comparators 2/252 DS12923 Rev 1