STM32H750VB STM32H750ZB STM32H750IB STM32H750XB 32-bit Arm Cortex -M7 480MHz MCUs, 128 Kbyte Flash, 1 Mbyte RAM, 46 com. and analog interfaces, crypto Datasheet - production data Features Includes ST state-of-the-art patented technology LQFP100 TFBGA240+25 UFBGA176+25 (14 x 14 mm) (14x14 mm) (10x10 mm) Core LQFP144 (20 x 20 mm) LQFP176 32-bit Arm Cortex -M7 core with double- (24 x 24 mm) precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache frequency up to 480 MHz, MPU, 1027 DMIPS/ Reset and power management 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP 3 separate power domains which can be instructions independently clock-gated or switched off: Memories D1: high-performance capabilities D2: communication peripherals and timers 128 Kbytes of Flash memory D3: reset/clock control/power management 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of 1.62 to 3.6 V application supply and I/Os DTCM RAM for time critical routines), POR, PDR, PVD and BOR 864 Kbytes of user SRAM, and 4 Kbytes of Dedicated USB power embedding a 3.3 V SRAM in Backup domain internal regulator to supply the internal PHYs Dual mode Quad-SPI memory interface Embedded regulator (LDO) with configurable running up to 133 MHz scalable output to supply the digital circuitry Flexible external memory controller with up to Voltage scaling in Run and Stop mode (6 32-bit data bus: configurable ranges) SRAM, PSRAM, NOR Flash memory Backup regulator (~0.9 V) clocked up to 133 MHz in synchronous mode Voltage reference for analog peripheral/V REF+ SDRAM/LPSDR SDRAM Low-power modes: Sleep, Stop, Standby and 8/16-bit NAND Flash memories V supporting battery charging BAT CRC calculation unit Low-power consumption Security V battery operating mode with charging BAT capability ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode CPU and domain power state monitoring pins 2.95 A in Standby mode (Backup SRAM OFF, General-purpose input/outputs RTC/LSE ON) Up to 168 I/O ports with interrupt capability February 2021 DS12556 Rev 6 1/336 This is information on a product in full production. www.st.comSTM32H750VB STM32H750ZB STM32H750IB STM32H750XB Clock management 2 operational amplifiers (7.3 MHz bandwidth) 1 digital filters for sigma delta modulator Internal oscillators: 64 MHz HSI, 48 MHz (DFSDM) with 8 channels/4 filters HSI48, 4 MHz CSI, 32 kHz LSI External oscillators: 4-48 MHz HSE, Graphics 32.768 kHz LSE LCD-TFT controller up to XGA resolution 3 PLLs (1 for the system clock, 2 for kernel Chrom-ART graphical hardware Accelerator clocks) with Fractional mode (DMA2D) to reduce CPU load Interconnect matrix Hardware JPEG Codec 3 bus matrices (1 AXI and 2 AHB) Up to 22 timers and watchdogs Bridges (5 AHB2-APB, 2 AXI2-AHB) 1 high-resolution timer (2.1 ns max 4 DMA controllers to unload the CPU resolution) 1 high-speed master direct memory access 2 32-bit timers with up to 4 IC/OC/PWM or controller (MDMA) with linked list support pulse counter and quadrature (incremental) encoder input (up to 240 MHz) 2 dual-port DMAs with FIFO 2 16-bit advanced motor control timers (up to 1 basic DMA with request router capabilities 240 MHz) Up to 35 communication peripherals 10 16-bit general-purpose timers (up to 240 MHz) 4 I2Cs FM+ interfaces (SMBus/PMBus) 5 16-bit low-power timers (up to 240 MHz) 4 USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART 2 watchdogs (independent and window) 6 SPIs, 3 with muxed duplex I2S audio class 1 SysTick timer accuracy via internal audio PLL or external RTC with sub-second accuracy and hardware clock, 1x I2S in LP domain (up to 150 MHz) calendar 4x SAIs (serial audio interface) Cryptographic acceleration SPDIFRX interface AES 128, 192, 256, TDES, SWPMI single-wire protocol master I/F HASH (MD5, SHA-1, SHA-2), HMAC MDIO Slave interface True random number generators 2 SD/SDIO/MMC interfaces (up to 125 MHz) 2 CAN controllers: 2 with CAN FD, 1 with Debug mode time-triggered CAN (TT-CAN) SWD & JTAG interfaces 2 USB OTG interfaces (1FS, 1HS/FS) crystal- 4-Kbyte Embedded Trace Buffer less solution with LPM and BCD Ethernet MAC interface with DMA controller 96-bit unique ID HDMI-CEC All packages are ECOPACK2 compliant 8- to 14-bit camera interface (up to 80 MHz) 11 analog peripherals 3 ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) 1 temperature sensor 2 12-bit D/A converters (1 MHz) 2 ultra-low-power comparators 2/336 DS12556 Rev 6