STM32H753xI 32-bit Arm Cortex -M7 480MHz MCUs, 2MB Flash, 1MB RAM, 46 com. and analog interfaces, crypto Datasheet - production data Features FBGA FBGA Core 32-bit Arm Cortex -M7 core with double- LQFP100 TFBGA100 UFBGA169 precision FPU and L1 cache: 16 Kbytes of data (1) (14 x 14 mm) (8 x 8 mm) (7 x 7 mm) LQFP144 TFBGA240+25 UFBGA176+25 and 16 Kbytes of instruction cache frequency (20 x 20 mm) (14 x 14 mm) (10 x 10 mm) up to 480 MHz, MPU, 1027 DMIPS/ LQFP176 (24 x 24 mm) 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP LQFP208 instructions (28 x 28 mm) Memories 1.62 to 3.6 V application supply and I/Os 2 Mbytes of Flash memory with read-while- POR, PDR, PVD and BOR write support Dedicated USB power embedding a 3.3 V 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. internal regulator to supply the internal PHYs 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Embedded regulator (LDO) with configurable 864 Kbytes of user SRAM, and 4 Kbytes of scalable output to supply the digital circuitry SRAM in Backup domain Voltage scaling in Run and Stop mode (6 Dual mode Quad-SPI memory interface configurable ranges) running up to 133 MHz Backup regulator (~0.9 V) Flexible external memory controller with up to Voltage reference for analog peripheral/V REF+ 32-bit data bus: SRAM, PSRAM, Low-power modes: Sleep, Stop, Standby and SDRAM/LPSDR SDRAM, NOR/NAND Flash V supporting battery charging memory clocked up to 100 MHz in BAT Synchronous mode Low-power consumption CRC calculation unit V battery operating mode with charging BAT Security capability CPU and domain power state monitoring pins ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode 2.95 A in Standby mode (Backup SRAM OFF, RTC/LSE ON) General-purpose input/outputs Clock management Up to 168 I/O ports with interrupt capability Internal oscillators: 64 MHz HSI, 48 MHz Reset and power management HSI48, 4 MHz CSI, 32 kHz LSI 3 separate power domains which can be External oscillators: 4-48 MHz HSE, independently clock-gated or switched off: 32.768 kHz LSE D1: high-performance capabilities 3 PLLs (1 for the system clock, 2 for kernel D2: communication peripherals and timers clocks) with Fractional mode D3: reset/clock control/power management April 2019 DS12117 Rev 7 1/356 This is information on a product in full production. www.st.comSTM32H753xI Interconnect matrix Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load 3 bus matrices (1 AXI and 2 AHB) Hardware JPEG Codec Bridges (5 AHB2-APB, 2 AXI2-AHB) Up to 22 timers and watchdogs 4 DMA controllers to unload the CPU 1 high-resolution timer (2.1 ns max 1 high-speed master direct memory access resolution) controller (MDMA) with linked list support 2 32-bit timers with up to 4 IC/OC/PWM or 2 dual-port DMAs with FIFO pulse counter and quadrature (incremental) 1 basic DMA with request router capabilities encoder input (up to 240 MHz) 2 16-bit advanced motor control timers (up to Up to 35 communication peripherals 240 MHz) 4 I2Cs FM+ interfaces (SMBus/PMBus) 10 16-bit general-purpose timers (up to 4 USARTs/4x UARTs (ISO7816 interface, 240 MHz) LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART 5 16-bit low-power timers (up to 240 MHz) 6 SPIs, 3 with muxed duplex I2S audio class 2 watchdogs (independent and window) accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz) 1 SysTick timer 4x SAIs (serial audio interface) RTC with sub-second accuracy and hardware calendar SPDIFRX interface SWPMI single-wire protocol master I/F Cryptographic acceleration MDIO Slave interface AES 128, 192, 256, TDES, 2 SD/SDIO/MMC interfaces (up to 125 MHz) HASH (MD5, SHA-1, SHA-2), HMAC 2 CAN controllers: 2 with CAN FD, 1 with True random number generators time-triggered CAN (TT-CAN) 2 USB OTG interfaces (1FS, 1HS/FS) crystal- Debug mode less solution with LPM and BCD SWD & JTAG interfaces Ethernet MAC interface with DMA controller 4-Kbyte Embedded Trace Buffer HDMI-CEC 96-bit unique ID 8- to 14-bit camera interface (up to 80 MHz) All packages are ECOPACK 2 compliant 11 analog peripherals Table 1. Device summary 3 ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS) Reference Part number 1 temperature sensor STM32H753VI, STM32H753ZI, STM32H753xI STM32H753II, STM32H753BI, 2 12-bit D/A converters (1 MHz) STM32H753XI, STM32H753AI 2 ultra-low-power comparators 2 operational amplifiers (7.3 MHz bandwidth) 1 digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters Graphics LCD-TFT controller up to XGA resolution 2/356 DS12117 Rev 7