STM32L100C6 STM32L100R8 STM32L100RB Ultra-low-power 32-bit MCU ARM -based Cortex -M3, 128KB Flash, 10KB SRAM, 2KB EEPROM, LCD, USB, ADC, DAC Datasheet production data Features Ultra-low-power platform 1.8 V to 3.6 V power supply LQFP64 UFQFPN48 10 x 10 mm 7 x 7 mm -40C to 85C temperature range 0.3 A Standby mode (2 wakeup pins) 0.9 A Standby mode + RTC Memories 0.57 A Stop mode (16 wakeup lines) Up to 128 Kbytes of Flash memory with 1.2 A Stop mode + RTC ECC Up to 10 Kbytes of RAM 9 A Low-power run mode Up to 2 Kbytes of true EEPROM with ECC 214 A/MHz Run mode 20-byte backup register 10 nA ultra-low I/O leakage < 8 s wakeup time LCD Driver for up to 8x28 segments Analog peripherals Core: 32-bit ARM Cortex -M3 CPU 12-bit ADC 1 Msps up to 20 channels From 32 kHz up to 32 MHz max 12-bit DAC 2 channels with output buffers 1.25 DMIPS/MHz (Dhrystone 2.1) Two ultra-low-power comparators Memory protection unit Seven DMA controller channels Reset and supply management Eight communication interface peripherals Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds One USB 2.0 Ultra-low-power POR/PDR Three USARTs (ISO 7816, IrDA) Programmable voltage detector (PVD) Two SPIs (16 Mbit/s) Two I2Cs (SMBus/PMBus) Clock sources Ten timers: 1 to 24 MHz crystal oscillator Six 16-bit timers with up to 4 IC/OC/PWM 32 kHz oscillator for RTC with calibration channels High-speed internal 16 MHz Two 16-bit basic timers Internal low-power 37 kHz RC Two watchdog timers (independent and Internal multispeed low-power 65 kHz to window) 4.2 MHz CRC calculation unit PLL for CPU clock and USB (48 MHz) All packages ECOPACK 2 Pre-programmed bootloader USART supported Development support Serial wire debug supported JTAG supported Up to 51 fast I/Os (42 I/Os 5V tolerant), all mappable on 16 external interrupt vectors August 2017 DocID024295 Rev 6 1/103 This is information on a product in full production. www.st.comContents STM32L100C6 STM32L100R8/RB Contents 1 Introduction 8 2 Description . 9 2.1 Device overview 10 2.2 Ultra-low-power device continuum .11 2.2.1 Performance . 11 2.2.2 Shared peripherals 11 2.2.3 Common system strategy . 11 2.2.4 Features . 11 3 Functional overview 12 3.1 Low-power modes 13 3.2 ARM Cortex -M3 core with MPU 17 3.3 Reset and supply management 18 3.3.1 Power supply schemes . 18 3.3.2 Power supply supervisor 18 3.3.3 Voltage regulator 19 3.3.4 Boot modes 19 3.4 Clock management . 20 3.5 Low-power real-time clock and backup registers . 22 3.6 GPIOs (general-purpose inputs/outputs) . 22 3.7 Memories . 23 3.8 DMA (direct memory access) 23 3.9 LCD (liquid crystal display) 23 3.10 ADC (analog-to-digital converter) . 24 3.10.1 Internal voltage reference (V ) . 24 REFINT 3.11 DAC (digital-to-analog converter) . 24 3.12 Ultra-low-power comparators and reference voltage 25 3.13 Routing interface . 25 3.14 Timers and watchdogs . 25 3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) . 26 3.14.2 Basic timers (TIM6 and TIM7) 26 3.14.3 SysTick timer . 26 2/103 DocID024295 Rev 6