STM32L4Q5xx Ultra-low-power Arm Cortex -M4 32-bit MCU+FPU, 150 DMIPS, 1-MB Flash, 320-KB SRAM, LCD-TFT, AES+PKA, ext SMPS Datasheet - production data Features Includes ST state-of-the-art patented technology UFQFPN48 LQFP48 (7 x 7 mm) (7 x 7 mm) LQFP64 (10 x 10 mm) Ultra-low-power with FlexPowerControl LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) 1.71 V to 3.6 V power supply UFBGA132 (7 x 7 mm) -40 C to 85/125 C temperature range UFBGA169 (7 x 7 mm) WLCSP100 (pitch 0.4 mm) Batch acquisition mode (BAM) 150 nA in VBAT mode: supply for RTC and 2 x Octo-SPI memory interfaces 32x32-bit backup registers General-purpose inputs/outputs 22 nA Shutdown mode (5 wakeup pins) Up to 136 fast I/Os, most 5 V-tolerant, up to 14 42 nA Standby mode (5 wakeup pins) I/Os with independent supply down to 1.08 V 190 nA Standby mode with RTC 2.95 A Stop 2 with RTC Performance benchmark 110 A/MHz Run mode (LDO mode) 1.25 DMIPS/MHz (Drystone 2.1) 41 A/MHz Run mode ( 3.3 V SMPS mode) 409.20 CoreMark (3.41 CoreMark/MHz 120 MHz) 5 s wakeup from Stop mode Brownout reset (BOR) in all modes except Energy benchmark Shutdown 285 ULPMarkCP score Core Up to 24 capacitive sensing channels Arm 32-bit Cortex -M4 CPU with FPU, Support touchkey, linear and rotary touch adaptive real-time accelerator (ART sensors Accelerator) allowing 0-wait-state execution from Flash memory, frequency up to 120 MHz, Clock management MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions 4 to 48 MHz crystal oscillator 32 kHz crystal oscillator for RTC (LSE) Memories Internal 16 MHz factory-trimmed RC (1%) 1-Mbyte Flash memory, 2 banks read-while- Internal low-power 32 kHz RC (5%) write, proprietary code readout protection Internal multispeed 100 kHz to 48 MHz 320 Kbytes of SRAM including 64 Kbytes with oscillator, auto-trimmed by LSE (better than hardware parity check 0.25 % accuracy) External memory interface for static memories Internal 48 MHz with clock recovery supporting SRAM, PSRAM, NOR, NAND and FRAM memories 3 PLLs for system clock, USB, audio, ADC November 2021 DS12902 Rev 3 1/312 This is information on a product in full production. www.st.comSTM32L4Q5xx Interconnect matrix LCD-TFT controller 1 AHB bus matrix 16x timers and watchdog 14-channel DMA controller 2 x 16-bit advanced motor-control 2 x 32-bit general purpose timers 23 communication peripherals 5 x 16-bit general purpose timers USB OTG 2.0 full-speed, LPM and BCD 2x 16-bit basic timers 2x SAIs (serial audio interface) 2x low-power 16-bit timers (available in Stop 4x I2C FM+(1 Mbit/s), SMBus/PMBus mode) 6x USARTs (ISO 7816, LIN, IrDA, modem) 2x watchdogs 3x SPIs (5x SPIs with the dual Octo-SPI) 1x SysTick timer CAN (2.0B Active) and 2x SDMMC RTC with hardware calendar, alarms and calibration 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) Cryptographic acceleration 8-/16-bit parallel synchronous data AES (128/256-bit key) input/output slave interface (PSSI) Public key accelerator (PKA) 11 analog peripherals (independent supply) True random generator 2x 12-bit ADC 5 Msps, up to 16-bit with CRC calculation unit hardware oversampling, 200 A/Msps 2x 12-bit DAC, low-power sample and hold HASH (SHA-256) hardware accelerator 2x operational amplifiers with built-in PGA Debug mode 2x ultra-low-power comparators Serial wire debug (SWD) 2x digital filters for sigma delta modulator JTAG 1x temperature sensor Embedded Trace Macrocell (ETM) Advanced graphics features 96-bit unique ID Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation Table 1. Device summary Reference Part numbers STM32L4Q5AG, STM32L4Q5CG, STM32L4Q5QG, STM32L4Q5RG, STM32L4Q5xx STM32L4Q5VG, STM32L4Q5ZG 2/312 DS12902 Rev 3