STM32L4R5xx STM32L4R7xx STM32L4R9xx Ultra-low-power Arm Cortex -M4 32-bit MCU+FPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, ext. SMPS Datasheet- production data Features Ultra-low-power with FlexPowerControl 1.71 V to 3.6 V power supply LQFP144 (20 20) UFBGA169 (7 x 7) WLCSP144 LQFP100 (14 x 14) UFBGA144 (10 x 10) -40 C to 85/125 C temperature range UFBGA132 (7 7) Batch acquisition mode (BAM) 305 nA in VBAT mode: supply for RTC and Internal multispeed 100 kHz to 48 MHz 32x32-bit backup registers oscillator, auto-trimmed by LSE (better than 33 nA Shutdown mode (5 wakeup pins) 0.25 % accuracy) 125 nA Standby mode (5 wakeup pins) Internal 48 MHz with clock recovery 420 nA Standby mode with RTC 3 PLLs for system clock, USB, audio, ADC 2.8 A Stop 2 with RTC RTC with HW calendar, alarms and calibration 110 A/MHz Run mode (LDO mode) Up to 24 capacitive sensing channels: support 43 A/MHz Run mode ( 3.3 V SMPS touchkey, linear and rotary touch sensors mode) Advanced graphics features 5 s wakeup from Stop mode Chrom-ART Accelerator (DMA2D) for Brownout reset (BOR) in all modes except enhanced graphic content creation shutdown Chrom-GRC (GFXMMU) allowing up to Interconnect matrix 20% of graphic resources optimization Core: Arm 32-bit Cortex -M4 CPU with FPU, MIPI DSI Host controller with two DSI adaptive real-time accelerator (ART lanes running at up to 500 Mbits/s each Accelerator) allowing 0-wait-state execution LCD-TFT controller from Flash memory, frequency up to 120 MHz, 16x timers: 2 x 16-bit advanced motor-control, MPU, 150 DMIPS/1.25 DMIPS/MHz 2 x 32-bit and 5 x 16-bit general purpose, 2x (Dhrystone 2.1), and DSP instructions 16-bit basic, 2x low-power 16-bit timers Performance benckmark (available in Stop mode), 2x watchdogs, 1.25 DMIPS/MHz (Drystone 2.1) SysTick timer 409.20 Coremark (3.41 Coremark/MHz Up to 136 fast I/Os, most 5 V-tolerant, up to 14 120 MHz) I/Os with independent supply down to 1.08 V Energy benckmark Memories 233 ULPMarkCP score 2-Mbyte Flash, 2 banks read-while-write, 56.5 ULPMarkPP score proprietary code readout protection Clock sources 640 Kbytes of SRAM including 64 Kbytes with hardware parity check 4 to 48 MHz crystal oscillator External memory interface for static 32 kHz crystal oscillator for RTC (LSE) memories supporting SRAM, PSRAM, Internal 16 MHz factory-trimmed RC (1%) NOR, NAND and FRAM memories Internal low-power 32 kHz RC (5%) 2 x OctoSPI memory interface 4x digital filters for sigma delta modulator January 2020 DS12023 Rev 5 1/307 This is information on a product in full production. www.st.comSTM32L4R5xx, STM32L4R7xx and STM32L4R9xx Rich analog peripherals (independent supply) 6x USARTs (ISO 7816, LIN, IrDA, modem) 12-bit ADC 5 Msps, up to 16-bit with 3x SPIs (5x SPIs with the dual OctoSPI) hardware oversampling, 200 A/Msps CAN (2.0B Active) and SDMMC 2x 12-bit DAC, low-power sample and hold 14-channel DMA controller 2x operational amplifiers with built-in PGA True random number generator 2x ultra-low-power comparators CRC calculation unit, 96-bit unique ID 20x communication interfaces 8- to 14-bit camera interface up to 32 MHz USB OTG 2.0 full-speed, LPM and BCD (black and white) or 10 MHz (color) 2x SAIs (serial audio interface) Development support: serial wire debug 4x I2C FM+(1 Mbit/s), SMBus/PMBus (SWD), JTAG, Embedded Trace Macrocell (ETM) Table 1. Device summary Reference Part numbers STM32L4R5VI, STM32L4R5QI, STM32L4R5ZI, STM32L4R5AI, STM32L4R5AG, STM32L4R5xx STM32L4R5QG, STM32L4R5VG, STM32L4R5ZG STM32L4R7xx STM32L4R7VI, STM32L4R7ZI, STM32L4R7AI STM32L4R9VI, STM32L4R9ZI, STM32L4R9AI, STM32L4R9AG, STM32L4R9VG, STM32L4R9xx STM32L4R9ZG 2/307 DS12023 Rev 5