STM32WB55xx STM32WB35xx Multiprotocol wireless 32-bit MCU Arm -based Cortex -M4 with FPU, Bluetooth 5.2 and 802.15.4 radio solution Datasheet - production data Features . Include ST state-of-the-art patented technology Radio UFQFPN48 VFQFPN68 2.4 GHz 7 x 7 mm solder pad 8 x 8 mm solder pad RF transceiver supporting Bluetooth 5.2 FBGA specification, IEEE 802.15.4-2011 PHY and MAC, supporting Thread and Zigbee 3.0 RX sensitivity: -96 dBm (Bluetooth Low WLCSP100 UFBGA129 Energy at 1 Mbps), -100 dBm (802.15.4) 0.4 mm pitch 0.5 mm pitch Programmable output power up to +6 dBm Core: Arm 32-bit Cortex -M4 CPU with FPU, with 1 dB steps adaptive real-time accelerator (ART Integrated balun to reduce BOM Accelerator) allowing 0-wait-state execution Support for 2 Mbps from Flash memory, frequency up to 64 MHz, Dedicated Arm 32-bit Cortex M0+ CPU MPU, 80 DMIPS and DSP instructions for real-time Radio layer Performance benchmark Accurate RSSI to enable power control 1.25 DMIPS/MHz (Drystone 2.1) Suitable for systems requiring compliance 219.48 CoreMark (3.43 CoreMark/MHz at with radio frequency regulations ETSI EN 64 MHz) 300 328, EN 300 440, FCC CFR47 Part 15 Energy benckmark and ARIB STD-T66 303 ULPMark CP score Support for external PA Available integrated passive device (IPD) Supply and reset management companion chip for optimized matching High efficiency embedded SMPS solution (MLPF-WB-01E3 or step-down converter with intelligent bypass MLPF-WB-02E3) mode Ultra-low-power platform Ultra-safe, low-power BOR (brownout reset) with five selectable thresholds 1.71 to 3.6 V power supply Ultra-low-power POR/PDR 40 C to 85 / 105 C temperature ranges Programmable voltage detector (PVD) 13 nA shutdown mode V mode with RTC and backup registers 600 nA Standby mode + RTC + 32 KB BAT RAM Clock sources 2.1 A Stop mode + RTC + 256 KB RAM 32 MHz crystal oscillator with integrated Active-mode MCU: < 53 A / MHz when RF trimming capacitors (Radio and CPU clock) and SMPS on 32 kHz crystal oscillator for RTC (LSE) Radio: Rx 4.5 mA / Tx at 0 dBm 5.2 mA Internal low-power 32 kHz (5%) RC (LSI1) Internal low-power 32 kHz (stability 500 ppm) RC (LSI2) April 2021 DS11929 Rev 11 1/193 This is information on a product in full production. www.st.comSTM32WB55xx STM32WB35xx Internal multispeed 100 kHz to 48 MHz 1x USB 2.0 FS device, crystal-less, BCD oscillator, auto-trimmed by LSE (better than and LPM 0.25% accuracy) Touch sensing controller, up to 18 sensors High speed internal 16 MHz factory LCD 8x40 with step-up converter trimmed RC (1%) 1x 16-bit, four channels advanced timer 2x PLL for system clock, USB, SAI and 2x 16-bit, two channels timer ADC 1x 32-bit, four channels timer Memories 2x 16-bit ultra-low-power timer Up to 1 MB Flash memory with sector 1x independent Systick protection (PCROP) against R/W 1x independent watchdog operations, enabling radio stack and 1x window watchdog application Security and ID Up to 256 KB SRAM, including 64 KB with hardware parity check Secure firmware installation (SFI) for Bluetooth Low Energy and 802.15.4 SW 20x32-bit backup register stack Boot loader supporting USART, SPI, I2C 3x hardware encryption AES maximum and USB interfaces 256-bit for the application, the Bluetooth OTA (over the air) Bluetooth Low Energy Low Energy and IEEE802.15.4 and 802.15.4 update Customer key storage / key manager Quad SPI memory interface with XIP services 1 Kbyte (128 double words) OTP HW public key authority (PKA) Rich analog peripherals (down to 1.62 V) Cryptographic algorithms: RSA, 12-bit ADC 4.26 Msps, up to 16-bit with Diffie-Helman, ECC over GF(p) hardware oversampling, 200 A/Msps True random number generator (RNG) 2x ultra-low-power comparator Sector protection against R/W operation Accurate 2.5 V or 2.048 V reference (PCROP) voltage buffered output CRC calculation unit System peripherals Die information: 96-bit unique ID Inter processor communication controller IEEE 64-bit unique ID. Possibility to derive (IPCC) for communication with Bluetooth 802.15.4 64-bit and Bluetooth Low Energy Low Energy and 802.15.4 48-bit EUI HW semaphores for resources sharing Up to 72 fast I/Os, 70 of them 5 V-tolerant between CPUs Development support 2x DMA controllers (7x channels each) Serial wire debug (SWD), JTAG for the supporting ADC, SPI, I2C, USART, QSPI, application processor SAI, AES, timers Application cross trigger with input / output 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode) Embedded Trace Macrocell for application 1x LPUART (low power) 2x SPI 32 Mbit/s All packages are ECOPACK2 compliant 2x I2C (SMBus/PMBus) 1x SAI (dual channel high quality audio) Table 1. Device summary Reference Part numbers STM32WB55CC, STM32WB55CE, STM32WB55CG, STM32WB55RC, STM32WB55RE, STM32WB55RG, STM32WB55xx STM32WB55VC, STM32WB55VE, STM32WB55VG, STM32WB55VY STM32WB35xx STM32WB35CC, STM32WB35CE 2/193 DS11929 Rev 11